Patents by Inventor Kuang-Hsin Chen
Kuang-Hsin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10205024Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.Type: GrantFiled: February 5, 2016Date of Patent: February 12, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ruey-Hsin Liu, Kuang-Hsin Chen, Chih-Hsin Ko, Shih-Fen Huang
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Patent number: 10199320Abstract: A method of fabricating an electronic package is provided, including: providing a carrier body having a first surface formed with a plurality of recessed portions, and a second surface opposing the first surface and interconnecting with the recessed portions; forming on the first surface of the carrier body an electronic structure that has a plurality of conductive elements received in the recessed portions correspondingly; and removing portion of the carrier body, with the conductive elements exposed from the second surface of the carrier body. Therefore, the carrier body is retained, and the fabrication cost is reduced since temporary material is required. The present invention further provides the electronic package thus fabricated.Type: GrantFiled: October 16, 2017Date of Patent: February 5, 2019Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ching-Wen Chiang, Kuang-Hsin Chen, Sheng-Li Lu, Hsien-Wen Chen
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Patent number: 10177036Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.Type: GrantFiled: February 9, 2018Date of Patent: January 8, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Tsung-Yu Chiang, Kuang-Hsin Chen, Hsin-Lung Chao, Chen Chu-Hsuan
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Patent number: 10163516Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The gate stack includes a first insulating layer, a charge trapping structure, a second insulating layer, and a gate electrode. The first insulating layer separates the semiconductor substrate from the charge trapping structure. The charge trapping structure is between the first insulating layer and the second insulating layer. The gate electrode is over the second insulating layer. The charge trapping structure includes a first layer and a second layer. The first layer includes zinc oxide, tin dioxide, titanium oxide, zinc tin oxide, indium oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxynitride, tin oxynitride, titanium oxynitride, zinc tin oxynitride, indium oxynitride, indium zinc oxynitride, or indium gallium zinc oxynitride.Type: GrantFiled: June 5, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: I-Chen Huang, Kuang-Hsin Chen, Yung-Hsien Wu, Wen-Chao Shen
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Publication number: 20180337123Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.Type: ApplicationFiled: July 27, 2018Publication date: November 22, 2018Inventors: Cheng-Chieh Lai, Meng-Ting Yu, Yung-Hsien Wu, Kuang-Hsin Chen
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Publication number: 20180337248Abstract: A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO2) layer is formed on a substrate. A titanium (Ti) layer is formed over the first hafnium oxide layer. A second hafnium oxide layer is formed over the titanium layer. The composite device structure is thermally annealed to produce a high-k dielectric structure having a hafnium titanium oxide (HfxTi1-xO2) layer interposed between the first hafnium oxide layer and the second hafnium oxide layer.Type: ApplicationFiled: July 31, 2018Publication date: November 22, 2018Inventors: I-Chen Huang, Yi-Ju Hsu, Chi-Wen Liu, Kuang-Hsin Chen, Yung-Hsien Wu, Chin-Yu Chen
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Patent number: 10134626Abstract: A semiconductor device is provided. The semiconductor device includes a doped isolation structure formed above a substrate, and the doped isolation structure includes a first doped portion and a second doped portion, and a doped concentration of the second doped portion is different from a doped concentration of the first doped portion. The semiconductor device also includes a first fin partially embedded in the doped isolation structure, and a sidewall surface of the first fin is in direct contact with the first doped portion. The semiconductor device includes a second fin partially embedded in the doped isolation structure, and the doped isolation structure is between the first fin and the second fin, and a sidewall surface of the second fin is in direct contact with the second doped portion.Type: GrantFiled: December 11, 2017Date of Patent: November 20, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Yu Chiang, Chung-Wei Lin, Kuang-Hsin Chen, Bor-Zen Tien
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Patent number: 10068984Abstract: A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO2) layer is formed on a substrate. A titanium (Ti) layer is formed over the first hafnium oxide layer. A second hafnium oxide layer is formed over the titanium layer. The composite device structure is thermally annealed to produce a high-k dielectric structure having a hafnium titanium oxide (HfxTi1-xO2) layer interposed between the first hafnium oxide layer and the second hafnium oxide layer.Type: GrantFiled: September 1, 2016Date of Patent: September 4, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Chen Huang, Yi-Ju Hsu, Chi-Wen Liu, Kuang-Hsin Chen, Yung-Hsien Wu, Chin-Yu Chen
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Patent number: 10062614Abstract: The present disclosure provides many different embodiments of a FinFET device that provide one or more improvements over the prior art. In one embodiment, a FinFET includes a semiconductor substrate and a plurality of fins having a first height and a plurality of fin having a second height on the semiconductor substrate. The second height may be less than the first height.Type: GrantFiled: June 30, 2017Date of Patent: August 28, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Joanna Chaw Yane Yin, Chi-Hsi Wu, Kuo-Chiang Ting, Kuang-Hsin Chen
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Patent number: 10056299Abstract: A method of manufacturing a semiconductor structure includes receiving a substrate; patterning a first active region, a second active region and an isolation between the first active region and the second active region over the substrate; disposing an inter-level dielectric (ILD) over the substrate; forming a first gate extended over the first active region, the isolation and the second active region; and forming a second gate over the first active region and the second active region, wherein the second gate includes a first section disposed over the first active region and a second section disposed over the second active region, a portion of the ILD is disposed between the first section and the second section.Type: GrantFiled: November 21, 2016Date of Patent: August 21, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wei-Shuo Ho, Tsung-Yu Chiang, Kuang-Hsin Chen
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Patent number: 10049973Abstract: A substrate structure is provided, which includes: a substrate body having opposite first and second surfaces; a plurality of conductive posts formed on the first surface of the substrate body and electrically connected to the substrate body; and a dielectric layer formed on the first surface of the substrate body for encapsulating the conductive posts, wherein one end surfaces of the conductive posts are exposed from the dielectric layer. Therefore, the present invention replaces the conventional silicon substrate with the dielectric layer so as to eliminate the need to fabricate the conventional TSVs (Through Silicon Vias) and thereby greatly reduce the fabrication cost. The present invention further provides an electronic package having the substrate structure and a fabrication method thereof.Type: GrantFiled: December 30, 2015Date of Patent: August 14, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ching-Wen Chiang, Kuang-Hsin Chen, Hsien-Wen Chen
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Patent number: 10008494Abstract: A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.Type: GrantFiled: January 11, 2017Date of Patent: June 26, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Chieh Lai, Kuang-Hsin Chen, Shih-Kai Fan, Yung-Hsien Wu, Yu-Hsun Chen
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Publication number: 20180174914Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.Type: ApplicationFiled: February 9, 2018Publication date: June 21, 2018Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen, Hsin-Lung Chao, Chen Chu-Hsuan
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Patent number: 9947766Abstract: A semiconductor device includes a substrate, a source/drain region, an etch stop layer, an oxide layer, an interlayer dielectric layer, and a contact plug. The source/drain region is in the substrate. The etch stop layer is over the source/drain region. The oxide layer is over the etch stop layer. The interlayer dielectric layer is over the oxide layer. The contact plug is electrically connected to the source/drain region through the interlayer dielectric layer, the oxide layer, and the etch stop layer.Type: GrantFiled: July 10, 2017Date of Patent: April 17, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen
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Publication number: 20180102278Abstract: A semiconductor device is provided. The semiconductor device includes a doped isolation structure formed above a substrate, and the doped isolation structure includes a first doped portion and a second doped portion, and a doped concentration of the second doped portion is different from a doped concentration of the first doped portion. The semiconductor device also includes a first fin partially embedded in the doped isolation structure, and a sidewall surface of the first fin is in direct contact with the first doped portion. The semiconductor device includes a second fin partially embedded in the doped isolation structure, and the doped isolation structure is between the first fin and the second fin, and a sidewall surface of the second fin is in direct contact with the second doped portion.Type: ApplicationFiled: December 11, 2017Publication date: April 12, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Yu CHIANG, Chung-Wei LIN, Kuang-Hsin CHEN, Bor-Zen TIEN
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Patent number: 9911658Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.Type: GrantFiled: December 5, 2016Date of Patent: March 6, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen, Hsin-Lung Chao, Chen Chu-Hsuan
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Publication number: 20180040550Abstract: A method of fabricating an electronic package is provided, including: providing a carrier body having a first surface formed with a plurality of recessed portions, and a second surface opposing the first surface and interconnecting with the recessed portions; forming on the first surface of the carrier body an electronic structure that has a plurality of conductive elements received in the recessed portions correspondingly; and removing portion of the carrier body, with the conductive elements exposed from the second surface of the carrier body. Therefore, the carrier body is retained, and the fabrication cost is reduced since temporary material is required. The present invention further provides the electronic package thus fabricated.Type: ApplicationFiled: October 16, 2017Publication date: February 8, 2018Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Ching-Wen Chiang, Kuang-Hsin Chen, Sheng-Li Lu, Hsien-Wen Chen
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Publication number: 20180012809Abstract: The present disclosure provides many different embodiments of a FinFET device that provide one or more improvements over the prior art. In one embodiment, a FinFET includes a semiconductor substrate and a plurality of fins having a first height and a plurality of fin having a second height on the semiconductor substrate. The second height may be less than the first height.Type: ApplicationFiled: June 30, 2017Publication date: January 11, 2018Inventors: Joanna Chaw Yane Yin, Chi-Hsi Wu, Kuo-Chiang Ting, Kuang-Hsin Chen
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Patent number: 9842761Abstract: A semiconductor device is provided. The semiconductor device includes a first fin partially surrounded by a first isolation structure and a second fin partially surrounded by a second isolation structure. The second isolation structure has a dopant concentration higher than that of the first isolation structure, and a height difference is between a top surface of the first isolation structure and a top surface of the second isolation structure.Type: GrantFiled: January 27, 2017Date of Patent: December 12, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Yu Chiang, Chung-Wei Lin, Kuang-Hsin Chen, Bor-Zen Tien
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Publication number: 20170330976Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The gate stack includes a first insulating layer, a charge trapping structure, a second insulating layer, and a gate electrode. The first insulating layer separates the semiconductor substrate from the charge trapping structure. The charge trapping structure is between the first insulating layer and the second insulating layer. The gate electrode is over the second insulating layer. The charge trapping structure includes a first layer and a second layer. The first layer includes zinc oxide, tin dioxide, titanium oxide, zinc tin oxide, indium oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxynitride, tin oxynitride, titanium oxynitride, zinc tin oxynitride, indium oxynitride, indium zinc oxynitride, or indium gallium zinc oxynitride.Type: ApplicationFiled: June 5, 2017Publication date: November 16, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: I-Chen HUANG, Kuang-Hsin CHEN, Yung-Hsien WU, Wen-Chao SHEN