Patents by Inventor Kuang-Hsiung Chen

Kuang-Hsiung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210035908
    Abstract: A semiconductor device package includes a first circuit layer, a second circuit layer, a first semiconductor die and a second semiconductor die. The first circuit layer includes a first surface and a second surface opposite to the first surface. The second circuit layer is disposed on the first surface of the first circuit layer. The first semiconductor die is disposed on the first circuit layer and the second circuit layer, and electrically connected to the first circuit layer and the second circuit layer. The second semiconductor die is disposed on the second circuit layer, and electrically connected to the second circuit layer.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Cheng LEE, Kuang Hsiung CHEN
  • Patent number: 10879159
    Abstract: A substrate, a semiconductor package thereof and a process of making the same are provided. The substrate comprises an upper circuit layer and a lower circuit layer, the upper circuit layer comprising at least one trace and at least one pad and the lower circuit layer comprising at least one trace and at least one pad, wherein the trace of the upper circuit layer and the trace of the lower circuit layer are not aligned.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: December 29, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Sheng-Ming Wang, Kuang-Hsiung Chen, Yu-Ying Lee
  • Publication number: 20200395275
    Abstract: A device includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion adjacent to and spaced apart from the die paddle, an outer lead portion opposite to the inner lead portion and a bridge portion between the inner lead portion and the outer lead portion. The inner lead portion has an upper bond section connected to the bridge portion and a lower support section below the upper bond section. A sum of a thickness of the upper bond section and a thickness of the lower support section is greater than a thickness of the bridge portion.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung CHEN, Chih-Hung HSU, Mei-Lin HSIEH, Yi-Cheng HSU, Yuan-Chun CHEN, Yu-Shun HSIEH, Ko-Pu WU
  • Patent number: 10734337
    Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: August 4, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuang-Hsiung Chen, Yu-Hsuan Tsai, Yu-Ying Lee, Sheng-Ming Wang, Wun-Jheng Syu
  • Patent number: 10643863
    Abstract: A semiconductor package includes a die and a patterned conductive layer electrically connected to the die. The patterned conductive layer includes a connection pad and a trace. The semiconductor package further includes an encapsulation layer encapsulating the die and the patterned conductive layer. The semiconductor package further includes an electrical connection element disposed on the connection pad and a protection layer including a sidewall portion surrounding the electrical connection element.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: May 5, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Kuang-Hsiung Chen, Shing-Cheng Liang, Pei-Yu Hsu
  • Publication number: 20200080841
    Abstract: An optical module includes: a carrier; an optical element disposed on the upper side of the carrier; and a housing disposed on the upper side of the carrier, the housing defining an aperture exposing at least a portion of the optical element, an outer sidewall of the housing including at least one singulation portion disposed on the upper side of the carrier, wherein the singulation portion of the housing is a first portion of the housing, and wherein the housing further includes a second portion and a surface of the singulation portion of the housing is rougher than a surface of the second portion of the housing.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ying-Chung CHEN, Hsun-Wei CHAN, Lu-Ming LAI, Kuang-Hsiung CHEN
  • Patent number: 10573624
    Abstract: A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: February 25, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, I-Cheng Wang, Wun-Jheng Syu
  • Patent number: 10515884
    Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: December 24, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Li-Chuan Tsai, Chih-Cheng Lee
  • Patent number: 10508910
    Abstract: An optical module includes a carrier, a light source disposed on an upper side of the carrier, an optical sensor disposed on the upper side of the carrier, and a housing disposed on the upper side of the carrier over the light source and the optical sensor. The housing defines a first aperture exposing at least a portion of the light source and a second aperture exposing at least a portion of the optical sensor. An outer sidewall of the housing includes at least one singulation portion adjacent to the upper side of the carrier and perpendicular to the upper side of the carrier.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: December 17, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ying-Chung Chen, Hsun-Wei Chan, Lu-Ming Lai, Kuang-Hsiung Chen
  • Patent number: 10446411
    Abstract: A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: October 15, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Yu-Tzu Peng
  • Publication number: 20190198469
    Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.
    Type: Application
    Filed: March 5, 2019
    Publication date: June 27, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung CHEN, Yu-Hsuan TSAI, Yu-Ying LEE, Sheng-Ming WANG, Wun-Jheng SYU
  • Publication number: 20190088626
    Abstract: A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.
    Type: Application
    Filed: November 16, 2018
    Publication date: March 21, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tien-Szu CHEN, Kuang-Hsiung CHEN, Sheng-Ming WANG, I-Cheng WANG, Wun-Jheng SYU
  • Patent number: 10224298
    Abstract: In one or more embodiments, a micro-electromechanical systems (MEMS) package structure comprises a MEMS die, a conductive pillar adjacent to the MEMS die, a package body and a binding layer on the package body. The package body encapsulates the MEMS die and the conductive pillar, and exposes a top surface of the conductive pillar. A glass transition temperature (Tg) of the package body is greater than a temperature for forming the binding layer (Tc).
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: March 5, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuang-Hsiung Chen, Yu-Hsuan Tsai, Yu-Ying Lee, Sheng-Ming Wang, Wun-Jheng Syu
  • Publication number: 20190067036
    Abstract: A semiconductor package includes a die and a patterned conductive layer electrically connected to the die. The patterned conductive layer includes a connection pad and a trace. The semiconductor package further includes an encapsulation layer encapsulating the die and the patterned conductive layer. The semiconductor package further includes an electrical connection element disposed on the connection pad and a protection layer including a sidewall portion surrounding the electrical connection element.
    Type: Application
    Filed: August 24, 2017
    Publication date: February 28, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: You-Lung YEN, Kuang-Hsiung CHEN, Shing-Cheng LIANG, Pei-Yu HSU
  • Patent number: 10157887
    Abstract: A semiconductor device package includes a first circuit layer, at least one electrical element, a first molding layer, an electronic component and a second molding layer. The at least one electrical element is disposed over a first surface of the first circuit layer and electrically connected to the first circuit layer. The first molding layer is disposed over the first surface of the first circuit layer. The first molding layer encapsulates an edge of the at least one electrical element, and a lower surface of the first molding layer and a lower surface of the at least one electrical element are substantially coplanar. The electronic component is disposed over a second surface of the first circuit layer and is electrically connected to the first circuit layer. The second molding layer is disposed over the second surface of the first circuit layer and encapsulates the electronic component.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: December 18, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, I-Cheng Wang, Wun-Jheng Syu
  • Publication number: 20180350626
    Abstract: A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.
    Type: Application
    Filed: August 13, 2018
    Publication date: December 6, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tien-Szu CHEN, Kuang-Hsiung CHEN, Sheng-Ming WANG, Yu-Ying LEE, Yu-Tzu PENG
  • Patent number: 10134683
    Abstract: A semiconductor device package includes a first circuit layer having a first surface and a second surface opposite the first side, a first electronic component, a shielding element, a shielding layer and a molding layer. The first electronic component is disposed over the first surface of the first circuit layer, and electrically connected to the first circuit layer. The shielding element is disposed over the first surface of the first circuit layer, and is electrically connected to the first circuit layer. The shielding element is disposed adjacent to at least one side of the first electronic component. The shielding layer is disposed over the first electronic component and the shielding element, and the shielding layer is electrically connected to the shielding element. The molding layer encapsulates the first electronic component, the shielding element and a portion of the shielding layer.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: November 20, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, I-Cheng Wang, Wun-Jheng Syu, Yu-Tzu Peng
  • Patent number: 10103110
    Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units which comprise a substrate unit; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures which comprise a semiconductor package structure comprising the substrate unit, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 ?m.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: October 16, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Sheng-Ming Wang, Kuang-Hsiung Chen, Yu-Ying Lee
  • Publication number: 20180261573
    Abstract: A semiconductor device package includes a first circuit layer, at least one electrical element, a first molding layer, an electronic component and a second molding layer. The at least one electrical element is disposed over a first surface of the first circuit layer and electrically connected to the first circuit layer. The first molding layer is disposed over the first surface of the first circuit layer. The first molding layer encapsulates an edge of the at least one electrical element, and a lower surface of the first molding layer and a lower surface of the at least one electrical element are substantially coplanar. The electronic component is disposed over a second surface of the first circuit layer and is electrically connected to the first circuit layer. The second molding layer is disposed over the second surface of the first circuit layer and encapsulates the electronic component.
    Type: Application
    Filed: March 9, 2017
    Publication date: September 13, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tien-Szu CHEN, Kuang-Hsiung CHEN, Sheng-Ming WANG, I-Cheng WANG, Wun-Jheng SYU
  • Publication number: 20180233457
    Abstract: A semiconductor device package includes a first circuit layer having a first surface and a second surface opposite the first side, a first electronic component, a shielding element, a shielding layer and a molding layer. The first electronic component is disposed over the first surface of the first circuit layer, and electrically connected to the first circuit layer. The shielding element is disposed over the first surface of the first circuit layer, and is electrically connected to the first circuit layer. The shielding element is disposed adjacent to at least one side of the first electronic component. The shielding layer is disposed over the first electronic component and the shielding element, and the shielding layer is electrically connected to the shielding element. The molding layer encapsulates the first electronic component, the shielding element and a portion of the shielding layer.
    Type: Application
    Filed: February 10, 2017
    Publication date: August 16, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tien-Szu CHEN, Kuang-Hsiung CHEN, Sheng-Ming WANG, I-Cheng WANG, Wun-Jheng SYU, Yu-Tzu PENG