Patents by Inventor Kuang-Hsiung Chen

Kuang-Hsiung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140327125
    Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 ?m.
    Type: Application
    Filed: May 2, 2014
    Publication date: November 6, 2014
    Inventors: Tien-Szu CHEN, Sheng-Ming WANG, Kuang-Hsiung CHEN, Yu-Ying LEE
  • Patent number: 8866311
    Abstract: The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: October 21, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Hsiang-Ming Feng, Yen-Hua Kuo
  • Publication number: 20140308778
    Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices is attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.
    Type: Application
    Filed: June 24, 2014
    Publication date: October 16, 2014
    Inventors: Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Hsiang-Ming Feng, Bing-Yun Cheng
  • Patent number: 8786062
    Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: July 22, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Chia-Hsiung Hsieh, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh
  • Patent number: 8779581
    Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices are attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: July 15, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Hsiang-Ming Feng, Bing-Yun Cheng
  • Publication number: 20140151876
    Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; (c) a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts are connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.
    Type: Application
    Filed: February 6, 2014
    Publication date: June 5, 2014
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Chia-Hsiung Hsieh, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh
  • Publication number: 20140084475
    Abstract: The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.
    Type: Application
    Filed: September 21, 2012
    Publication date: March 27, 2014
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Hsiang-Ming Feng, Yen-Hua Kuo
  • Publication number: 20140021636
    Abstract: A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.
    Type: Application
    Filed: September 23, 2013
    Publication date: January 23, 2014
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh, Ming Chiang Lee, Bernd Karl Appelt
  • Patent number: 8592962
    Abstract: A Quad Flat No Leads (QFN) package includes a lead frame, a chip, an encapsulant, and a protective layer. The lead frame includes a plurality of leads. Each of the leads has a lower surface that is divided into a contact area and a non-contact area. The chip is configured on and electrically connected to the lead frame. The encapsulant encapsulates the chip and the leads and fills spaces between the leads. The contact areas and the non-contact areas of the leads are exposed by the encapsulant. The protective layer covers the non-contact areas of the leads.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: November 26, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung Chen, Sheng-Ming Wang, Hsiang-Ming Feng, Yu-Ying Lee, Mei-Lin Hsieh
  • Patent number: 8569894
    Abstract: A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: October 29, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh, Ming Chiang Lee, Bernd Karl Appelt
  • Patent number: 8367473
    Abstract: A chip package structure includes a substrate, a die, and a package body. The substrate includes a single patterned, electrically conductive layer, and a patterned dielectric layer adjacent to an upper surface of the electrically conductive layer. A part of a lower surface of the electrically conductive layer forms first contact pads for electrical connection externally. The patterned dielectric layer exposes a part of the upper surface of the electrically conductive layer to form second contact pads. The electrically conductive layer exposes the lower surface of the patterned dielectric layer on a lower periphery of the substrate. The die is electrically connected to the second contact pads, the patterned dielectric layer and the die being positioned on the same side of the electrically conductive layer. The package body is disposed adjacent to the upper surface of the electrically conductive layer and covers the patterned dielectric layer and the die.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: February 5, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Shih-Fu Huang, Yuan-Chang Su, Chia-Cheng Chen, Ta-Chun Lee, Kuang-Hsiung Chen
  • Patent number: 8330267
    Abstract: A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: December 11, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung Chen, Pao-Ming Hsieh, Yuan-Chang Su, Shih-Fu Huang, Bernd Karl Appelt
  • Patent number: 8309400
    Abstract: The package structure includes a metal sheet having a first central block, a plurality of first metal blocks, a second central block and a plurality of second metal blocks, a first finish layer and a second finish layer, at least a chip disposed on the metal sheet and a package body encapsulating the chip. The package structure may further include at least an area block for wire routing.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: November 13, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Bernd Karl Appelt, Kay Essig, Yuan-Chang Su, Chun-Che Lee, Kuang-Hsiung Chen
  • Patent number: 8304865
    Abstract: A leadframe including a die pad, leads, an outer frame, connecting bars and grounding bars is provided. Each of the grounding bars is suspended between two connecting bars by being connected with branches of the two connecting bars, such that the grounding bars are spaced by the die pad. The leadframe and the chip package of the present invention can permit a great design variation.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: November 6, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yueh-Chen Hsu, Mei-Lin Hsieh, Chih-Hung Hsu, Kuang-Hsiung Chen, Yi-Cheng Hsu
  • Patent number: 8288869
    Abstract: A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: October 16, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Shih-Fu Huang, Yuan-Chang Su, Chia-Cheng Chen, Kuang-Hsiung Chen, Ming-Chiang Lee, Bernd Karl Appelt, Chia-Hsiung Hsieh
  • Patent number: 8273445
    Abstract: A reinforced assembly carrier is provided. A supporting frame made of molding compound is formed on the edge area of the upper surface and/or on the edge area of the lower surface of the assembly carrier thereby enhancing the mechanical strength of the assembly carrier.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: September 25, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ren Yih Jeng, Kuang Hsiung Chen, Chun Hung Hsu
  • Publication number: 20120217642
    Abstract: A semiconductor device package including a substrate, a first device module, a second device module, and an package body. The first device module and the second device module are disposed side-by-side on a carrier surface of the substrate. The first device module includes first connecting elements provided with a first pitch. The second device module includes second connecting elements provided with a second pitch. The first pitch is different from the second pitch. The package body is disposed on the carrier surface and covers the first chip module and the second chip module. The package body includes first openings exposing the first connecting elements and second openings exposing the second connecting elements.
    Type: Application
    Filed: February 28, 2011
    Publication date: August 30, 2012
    Inventors: Yu-Ching Sun, Fa-Hao Wu, Kuang-Hsiung Chen, Chi-Tsung Chiu
  • Publication number: 20120112338
    Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices are attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.
    Type: Application
    Filed: November 7, 2011
    Publication date: May 10, 2012
    Inventors: Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Hsiang-Ming Feng, Bing-Yun Cheng
  • Publication number: 20120104584
    Abstract: A Quad Flat No Leads (QFN) package includes a lead frame, a chip, an encapsulant, and a protective layer. The lead frame includes a plurality of leads. Each of the leads has a lower surface that is divided into a contact area and a non-contact area. The chip is configured on and electrically connected to the lead frame. The encapsulant encapsulates the chip and the leads and fills spaces between the leads. The contact areas and the non-contact areas of the leads are exposed by the encapsulant. The protective layer covers the non-contact areas of the leads.
    Type: Application
    Filed: August 29, 2011
    Publication date: May 3, 2012
    Inventors: Kuang-Hsiung Chen, Sheng-Ming Wang, Hsiang-Ming Feng, Yu-Ying Lee, Mei-Lin Hsieh
  • Publication number: 20120091569
    Abstract: The package structure includes a metal sheet having a first central block, a plurality of first metal blocks, a second central block and a plurality of second metal blocks, a first finish layer and a second finish layer, at least a chip disposed on the metal sheet and a package body encapsulating the chip. The package structure may further include at least an area block for wire routing.
    Type: Application
    Filed: October 15, 2010
    Publication date: April 19, 2012
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Bernd Karl Appelt, Kay Essig, Yuan-Chang Su, Chun-Che Lee, Kuang-Hsiung Chen