Patents by Inventor Kuang Liu

Kuang Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190378712
    Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset specifying a plurality features to be formed on the workpiece. A first patterning of a hard mask of the workpiece is performed based on a first set of features of the plurality of features, and a first spacer material is deposited on a sidewall of the patterned hard mask. A second patterning is performed based on a second set of features, and a second spacer material is deposited on a sidewall of the first spacer material. A third patterning is performed based on a third set of features. A portion of the workpiece is selectively processed using a pattern defined by a remainder of at least one of the patterned hard mask layer, the first spacer material, or the second spacer material.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 12, 2019
    Inventors: Yung-Sung YEN, Chun-Kuang CHEN, Ko-Bin KAO, Ken-Hsien HSIEH, Ru-Gun LIU
  • Patent number: 10499461
    Abstract: A thermal heat for integrated circuit die processing is described that includes a thermal barrier. In one example, the thermal head has a ceramic heater configured to carry an integrated circuit die, a metal base, and a thermal barrier between the heater and the base.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Mohit Mamodia, Kyle Yazzie, Dingying Xu, Kuang Liu, Paul J. Diglio, Pramod Malatkar
  • Publication number: 20190355731
    Abstract: In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a pad stack over a semiconductor substrate, where the pad stack includes a lower pad layer and an upper pad layer. An isolation structure having a pair of isolation segments separated in a first direction by the pad stack is formed in the semiconductor substrate. The upper pad is removed to form an opening, where the isolation segments respectively have opposing sidewalls in the opening that slant at a first angle. A first etch is performed that partially removes the lower pad layer and isolation segments in the opening so the opposing sidewalls slant at a second angle greater than the first angle. A second etch is performed to round the opposing sidewalls and remove the lower pad layer from the opening. A floating gate is formed in the opening.
    Type: Application
    Filed: May 16, 2018
    Publication date: November 21, 2019
    Inventors: Hung-Ling Shih, Chieh-Fei Chiu, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair, Shih Kuang Yang
  • Publication number: 20190348298
    Abstract: In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.
    Type: Application
    Filed: July 22, 2019
    Publication date: November 14, 2019
    Inventors: Su-Hao Liu, Tsan-Chun Wang, Liang-Yin Chen, Jing-Huei Huang, Lun-Kuang Tan, Huicheng Chang
  • Patent number: 10455685
    Abstract: An electronic device may include a circuit board, and the circuit board may include a dielectric material. A socket may be coupled to a first side of the circuit board, and the socket may be configured to receive a semiconductor package. A backing plate may be positioned on a second side of the circuit board. A spacer may be positioned between the backing plate and the circuit board. The spacer may alter the profile of the socket to provide a curved profile to the socket. The spacer may displace a portion of the socket in a first direction, for instance when the spacer is coupled between the backing plate and the circuit board.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Steven A. Klein, Kuang Liu, Thomas A. Boyd, Luis Gil Rangel, Muffadal Mukadem, Shelby A. Ferguson, Francis Toth, Jr., Eric Buddrius, Ralph V. Miele, Sriram Srinivasan, Jeffory L. Smalley
  • Publication number: 20190305107
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a dielectric layer, a contact plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The dielectric layer is positioned over the gate structure and the source/drain structure. The contact plug is positioned passing through the dielectric layer. The contact plug includes a first metal compound including one of group III elements, group IV elements, group V elements or a combination thereof.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Inventors: Kuo-Ju CHEN, Su-Hao LIU, Chun-Hao KUNG, Liang-Yin CHEN, Huicheng CHANG, Kei-Wei CHEN, Hui-Chi HUANG, Kao-Feng LIAO, Chih-Hung CHEN, Jie-Huang HUANG, Lun-Kuang TAN, Wei-Ming YOU
  • Publication number: 20190288068
    Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.
    Type: Application
    Filed: June 6, 2019
    Publication date: September 19, 2019
    Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Maio Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
  • Patent number: 10388523
    Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset specifying a plurality features to be formed on the workpiece. A first patterning of a hard mask of the workpiece is performed based on a first set of features of the plurality of features, and a first spacer material is deposited on a sidewall of the patterned hard mask. A second patterning is performed based on a second set of features, and a second spacer material is deposited on a sidewall of the first spacer material. A third patterning is performed based on a third set of features. A portion of the workpiece is selectively processed using a pattern defined by a remainder of at least one of the patterned hard mask layer, the first spacer material, or the second spacer material.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: August 20, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Sung Yen, Chun-Kuang Chen, Ko-Bin Kao, Ken-Hsien Hsieh, Ru-Gun Liu
  • Patent number: 10388784
    Abstract: A power chip and a transistor structure thereof are provided. The transistor structure includes a semiconductor substrate, a plurality of gate structures, a plurality of first doped regions and a second doped region. The gate structures are disposed on the semiconductor substrate. The first doped regions are formed respectively in a plurality of first areas surrounded by the gate structures. The second doped region is formed in a second area among the gate structures. Each of the gate structures is arranged in an enclosed ring, and the shape of each of the gate structures is octagon.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: August 20, 2019
    Assignee: Excelliance MOS Corporation
    Inventor: Chu-Kuang Liu
  • Publication number: 20190244901
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of gate structures extending in a first direction over a substrate between a plurality of source/drain regions. A lower power rail is formed extending in a second direction perpendicular to the first direction. A first connection pin is formed to be electrically coupled to one of the plurality of source/drain regions and to the lower power rail. The first connection pin is formed according to a cut mask having cut regions that define opposing ends of the first connection pin. An upper power rail is formed directly over the lower power rail and extending in the second direction. The upper power rail is electrically coupled to the first connection pin.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 8, 2019
    Inventors: Shih-Wei Peng, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Yung-Sung Yen
  • Publication number: 20190229054
    Abstract: A package device includes a circuit layer, at least one conductive segment, an encapsulant and a redistribution layer. The conductive segment is disposed on the circuit layer and has a first surface and a second surface. The encapsulant encapsulates at least a portion of the conductive segment and has a first upper surface. A first portion of the first surface and at least a portion of the second surface of the conductive segment are disposed above the first upper surface of the encapsulant. The redistribution layer is disposed on the encapsulant, the first portion of the first surface of the conductive segment, and the second surface of the conductive segment.
    Type: Application
    Filed: January 25, 2018
    Publication date: July 25, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen-Long LU, Jen-Kuang FANG, Min Lung HUANG, Chan Wen LIU, Ching Kuo HSU
  • Patent number: 10361094
    Abstract: In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Hao Liu, Tsan-Chun Wang, Liang-Yin Chen, Jing-Huei Huang, Lun-Kuang Tan, Huicheng Chang
  • Publication number: 20190211295
    Abstract: A movable cell incubator contains: a body, a first lid, a second lid and an electric control unit. The body includes a first internal space, a refrigeration room, and an airtight culture room. The first lid airtightly covers the culture room, the second lid airtightly covers the refrigeration room, and the control unit includes a microprocessor, a power module, a digital/analog conversion module defined between a microprocessor and the power module, a heating module controlling temperature of the culture room, a cooling module supplying cold source to the refrigeration room, a peristaltic pump module, a flow sensing module, a CO2 detective supply module supplying CO2 to the culture room, and a setting display module exposing and fixed on the first lid, with the peristaltic pump module aseptically connected between cell culture media and cell culture bag by multiple conveying tubes.
    Type: Application
    Filed: March 19, 2019
    Publication date: July 11, 2019
    Inventor: LUN-KUANG LIU
  • Patent number: 10347720
    Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Miao Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
  • Patent number: 10312109
    Abstract: Patterning techniques are disclosed that can relax overlay requirements and/or increase integrated circuit design flexibility. An exemplary method includes forming a first set of fins and a second set of fins having different etch sensitivities on a material layer. The fins of the second set of fins are interspersed between the fins of the first set of fins. A first patterning process removes a subset of the first set of fins and a portion of the material layer underlying the subset of the first set of fins. The first patterning process avoids substantial removal of an exposed portion of the second set of fins. A second patterning process removes a subset of the second set of fins and a portion of the material layer underlying the subset of the second set of fins. The second patterning process avoids substantial removal of an exposed portion of the first set of fins.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Yuan Tseng, Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Ru-Gun Liu, Tsai-Sheng Gau, Wei-Liang Lin
  • Publication number: 20190157148
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a first contact plug and a first via plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The first contact plug is positioned over the source/drain structure. The first via plug is positioned over the first contact plug. The first via plug includes a first group IV element.
    Type: Application
    Filed: June 28, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Po HSIEH, Su-Hao LIU, Hong-Chih LIU, Jing-Huei HUANG, Jie-Huang HUANG, Lun-Kuang TAN, Huicheng CHANG, Liang-Yin CHEN, Kuo-Ju CHEN
  • Publication number: 20190142180
    Abstract: An inflation identification connector and an air mattress system having the same is provided. The inflation identification connector is insertable into a connection seat of a gas delivery host. The connection seat has a light detection component coupled to a controller disposed in the gas delivery host. The inflation identification connector includes a body and an identification structure. The detection result of the light detection component depends on the identification structure and thus is conducive to identification. Upon its insertion into the connection seat, the inflation identification connector is identified by the gas delivery host, enhancing ease of use and protecting manual operation against mistakes. The gas delivery host is not only applicable to different types of air mattresses but also conducive to streamlined management of the air mattress system and reduction of management costs and risks.
    Type: Application
    Filed: October 30, 2018
    Publication date: May 16, 2019
    Inventors: DAVID HUANG, WEN-BIN SHEN, JU-CHIEN CHENG, MING-HENG HSIEH, FU-WEI CHEN, CHIH-KUANG CHANG, YI-LING LIU, SHENG-WEI LIN, CHUNG-YI LIN
  • Publication number: 20190139746
    Abstract: A fabrication system for fabricating an IC is provided which includes a processing tool, a computation device and a FDC system. The processing tool includes an electrode and an RF sensor to execute a semiconductor manufacturing process to fabricate the IC. The RF sensor wirelessly detects the intensity of the RF signal. The computation device extracts statistical characteristics based on the detection of the intensity of the RF signal. The FDC system determines whether or not the intensity of the RF signal meets a threshold value or a threshold range according to the extracted statistical characteristics. When the detected intensity of the RF signal exceeds the threshold value or the threshold range, the FDC system notifies the processing tool to adjust the RF signal or stop tool to check parts damage.
    Type: Application
    Filed: February 22, 2018
    Publication date: May 9, 2019
    Inventors: Wun-Kai TSAI, Wen-Che LIANG, Chao-Keng LI, Zheng-Jie XU, Chih-Kuo CHANG, Sing-Tsung LI, Feng-Kuang WU, Hsu-Shui LIU
  • Publication number: 20190044265
    Abstract: Apparatuses, systems and methods associated with connector design for mating with integrated circuit packages are disclosed herein. In embodiments, a connector for mating with an integrated circuit (IC) package may include a housing with a recess to receive a portion of the IC package and a contact coupled to the housing and that extends into the recess. The contact may include a main body that extends from the housing into the recess and a curved portion that extends from an end of the main body, wherein the curved portion loops back and contacts the main body. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 9, 2018
    Publication date: February 7, 2019
    Inventors: FEIFEI CHENG, EMAD AL-MOMANI, AHMET DURGUN, KUANG LIU
  • Publication number: 20180340142
    Abstract: A movable cell incubator contains: a body, a first lid, a second lid, and an electric control unit. The body includes a first internal space, a refrigeration room, and an airtight culture room. The first lid airtightly covers the culture room, the second lid airtightly covers the refrigeration room, and the control unit includes a microprocessor, a power module, a digital/analog conversion module defined between a microprocessor and the power module, a heating module controlling temperature of the culture room, a cooling module supplying cold source to the refrigeration room, a peristaltic pump module, a flow sensing module, a CO2 detective supply module supplying CO2 to the culture room, and a setting display module exposing and fixed on the first lid, with the peristaltic pump module aseptically connected between cell culture media and cell culture bag by multiple conveying tubes.
    Type: Application
    Filed: May 25, 2017
    Publication date: November 29, 2018
    Inventor: LUN-KUANG LIU