Patents by Inventor Kuei-An LIN

Kuei-An LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162108
    Abstract: A knockdown heat sink structure includes a carrier body with a high-temperature section in contact with at least one heat source. A non-high-temperature section of the carrier body has a first radiating fin assembly, while a higher second radiating fin assembly is on the high-temperature section. The second radiating fin assembly has a first part higher than the height of the first radiating fin assembly, and a second part that outward spreads and extends from a top end of the first part and covers the first assembly without touching it, creating a spacing flow way. Therefore, the structure increases the heat dissipation area for the high-temperature section, allowing for faster heat dissipation.
    Type: Application
    Filed: May 11, 2023
    Publication date: May 16, 2024
    Inventors: Yuan-Yi Lin, Fu-Kuei Chang
  • Patent number: 11983848
    Abstract: Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: May 14, 2024
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Lung Jen, Pei-Kuei Tsung, Chih-Wei Chen, Yao-Sheng Wang, Shih-Che Chen, Yu-Sheng Lin, Chih-Wen Goo, Shih-Chin Lin, Tsung-Shian Huang, Ying-Chieh Chen
  • Patent number: 11973001
    Abstract: Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Shen Yeh, Chin-Hua Wang, Chia-Kuei Hsu, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20240120160
    Abstract: A keyswitch includes a board, a cap located above the board, a membrane circuit board disposed on the board to make first and second engaging structures of the board protrude from first and second holes of the membrane circuit board respectively, and a lifting device. The lifting device is connected to the cap and the board and includes first and second support members. The first support member is movably connected to the cap and has a pivot end portion. The pivot end portion is movably connected to the first and second engaging structures and has a first abutting portion extending toward edges of the first and second holes along a pivot axis of the first engaging structure. The first abutting portion abuts on the membrane circuit board. The second support member rotatably intersects with the first support member and is movably connected to the cap and the board.
    Type: Application
    Filed: September 26, 2023
    Publication date: April 11, 2024
    Applicant: DARFON ELECTRONICS CORP.
    Inventors: Po-Wei Tsai, Wun-Huei Wang, Kuei-Lin Teng
  • Patent number: 11953740
    Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 11947173
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Publication number: 20240096822
    Abstract: A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Chia-Kuei HSU, Ming-Chih YEW, Shu-Shen YEH, Che-Chia YANG, Po-Yao LIN, Shin-Puu JENG
  • Patent number: 11923353
    Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jen Lai, Chung-Yi Lin, Hsi-Kuei Cheng, Chen-Shien Chen, Kuo-Chio Liu
  • Publication number: 20240070582
    Abstract: An apparatus for estimating a fair value of a SPP includes a sunshine simulation system for generating a peak sun hour; a photovoltaic (PV) yield system for measuring a total power loss rate and generating an estimated energy-production-hours database; and a financial pricing system for generating a series of cash flows and discount factors. The financial pricing system computes a series of present values which are the product of the cash flows and the discount factors, and sums up all the present values to obtain an estimated value of the SPP. Since the apparatus for estimating SPP value takes the real power generation condition of the SPP and the real market economic condition into consideration, so that the apparatus can generate a pricing result even closer to the real market.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Applicant: Guang Teng Renewable Energy Co., Ltd.
    Inventors: An-Hsing CHANG, Ming-Che CHUANG, Shih-Kuei LIN, Che-Yi YIN
  • Patent number: 11917795
    Abstract: A heat sink structure includes a base seat and at least one heat dissipation unit. The base seat has a first face and a second face. At least one extension column extends from the second face of the base seat. The heat dissipation unit is disposed above the base seat and spaced from the base seat by a gap. The extension column serves to restrict or secure the heat dissipation unit in horizontal and vertical directions. The heat dissipation unit with different structures provides multiple heat dissipation features to enhance the entire heat dissipation performance.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: February 27, 2024
    Assignee: Asia Vital Components Co., Ltd.
    Inventors: Yuan-Yi Lin, Fu-Kuei Chang
  • Publication number: 20240012213
    Abstract: A photonic integrated circuit has a central region and a peripheral region surrounding the central region. The photonic integrated circuit includes a semiconductor layer, a seal ring structure, and a plurality of silicon waveguides. The seal ring structure is disposed on the semiconductor layer. The seal ring structure is located in the peripheral region and has at least one recess recessing towards the central region from a top view. The seal ring structure is a continuous structure from the top view. The silicon waveguides are embedded in the semiconductor layer.
    Type: Application
    Filed: September 21, 2023
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Ming Weng, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 11846862
    Abstract: A lighting structure includes a surface cover plate, a lighting module, a light adjustment layer, an optical adhesive layer and an electronic paper display module. The surface cover plate has a visible area and a black bezel. The lighting module has a light guide plate and point light sources. The light adjustment layer has an optical thinning region and a frame-shaped adhesive. The optical thinning region is less than the light guide plate in refractive index. The surface cover plate and the lighting module are adhered by the frame-shaped adhesive. The optical thinning region is disposed on an upper surface of the light guide plate. The optical adhesive layer has a refractive index equal to or greater than a refractive index of the light guide plate. The electronic paper display module is disposed under the lighting module.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: December 19, 2023
    Assignee: YOUNG FAST OPTOELECTRONICS CO., LTD.
    Inventors: Chih-Chiang Pai, Meng-Kuei Lin, Chin-An Tsai, Li-Yeh Yang, Yi-Jing Huang, Chih-Jung Tsui
  • Publication number: 20230400784
    Abstract: A lithography system includes a table body, a wafer stage, a first sliding member, a second sliding member, a first cable, a first bracket, a rail guide, and a first protective film. The first sliding member is coupled to the wafer stage. The second sliding member is coupled to an edge of the table body, in which the first sliding member is coupled to a track of the second sliding member. The first bracket fixes the first cable, the first bracket being coupled to a roller structure, in which the roller structure includes a body and a wheel coupled to the body. The rail guide confines a movement of the wheel of the roller structure. The first protective film is adhered to a surface of the rail guide, in which the roller structure is moveable along the first protective film on the surface of the rail guide.
    Type: Application
    Filed: July 28, 2023
    Publication date: December 14, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Hua WANG, Chueh-Chi KUO, Kuei-Lin HO, Zong-You YANG, Cheng-Wei SUN, Wei-Yuan CHEN, Cheng-Chieh CHEN, Heng-Hsin LIU, Li-Jui CHEN
  • Publication number: 20230395683
    Abstract: A post-deposition treatment can be applied to an atomic layer deposition (ALD)-deposited film to seal one or more seams at the surface. The seam-top treatment can physically merge the two sides of the seam, so that the surface behaves as a continuous material to allow etching at a substantially uniform rate across the surface of the film. The seam-top treatment can be used to merge seams in ALD-deposited films within semiconductor structures, such as gate-all-around field effect transistors (GAAFETs).
    Type: Application
    Filed: June 6, 2022
    Publication date: December 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Lin CHAN, Fu-Ting YEN, Yu-Yun PENG, Keng-Chu LIN
  • Patent number: 11832418
    Abstract: A liquid cooling head includes a chassis, an inlet channel, a thermally-conducting structure, a liquid gathering structure, a drain channel and a pump set. The chassis includes a lower chamber and an upper chamber communicated with the lower chamber through a connection opening. The inlet channel is disposed on one side of the chassis, and communicated with the upper chamber for radiating the heat of the working fluid away. The thermally-conducting structure is disposed in the lower chamber for gathering the working fluid passed through the thermally-conducting structure. The drain channel is disposed on one side of the chassis to be communicated with the lower chamber. The pump set for pushing the working fluid in the lower chamber to discharge the working fluid outwards from the drain channel.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: November 28, 2023
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Chien-Yu Chen, Tian-Li Ye, Yu Chen, Jen-Hao Lin, Chien-An Chen, Yun-Kuei Lin
  • Publication number: 20230373441
    Abstract: A heating sticker includes a protective layer, a thermogenic layer, an electrode layer, a cover layer and an adhesive layer, which are superposed in order. The thermogenic layer is a conductive film with transparent carbon nanobuds and defined with a heating area and a non-heating area. The heating area is disposed with insulative grooves. The non-heating area is distributed with micro blocks which are arranged insulatively. The electrode layer has a conductive wire and a ground wire. The conductive wire surrounds the heating area in a non-closed shape. The ground wire is located between the front end and the rear end of the conductive wire and connected to a periphery of the heating area. Conductivity of each of the conductive wire and the ground wire is higher than conductivity of the thermogenic layer. An outer surface of the cover layer is a modified surface which is treated with plasma.
    Type: Application
    Filed: May 19, 2022
    Publication date: November 23, 2023
    Applicant: Young Fast Optoelectronics Co., Ltd.
    Inventors: Chih-Chiang Pai, Meng-Kuei Lin, Chun-Hao Huang, Jung-Han Liu, Chih-Jung Tsui
  • Publication number: 20230367062
    Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
  • Patent number: 11809000
    Abstract: A photonic integrated circuit includes a substrate, an interconnection layer, and a plurality of silicon waveguides. The interconnection layer is over the substrate. The interconnection layer includes a seal ring structure and an interconnection structure surrounded by the seal ring structure. The seal ring structure has at least one recess from a top view. The recess concaves towards the interconnection structure. The silicon waveguides are embedded in the substrate.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: November 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Ming Weng, Hua-Kuei Lin, Che-Hsiang Hsu
  • Publication number: 20230326988
    Abstract: A device includes at least one semiconductor unit which includes a first source/drain portion, a second source/drain portion, at least one nanosheet segment which is disposed to interconnect the first and second source/drain portions, a gate portion disposed around the at least one nanosheet segment, and a first inner spacer portion and a second inner spacer portion which are disposed to separate the gate portion from the first and second source/drain portions, respectively. Each of the first and second inner spacer portions has a carbon-rich region which confronts the gate portion.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Ting YEN, Kuei-Lin CHAN, Yu-Yun PENG
  • Patent number: 11782350
    Abstract: A lithography system includes a table body, a wafer stage, a first sliding member, a second sliding member, a first cable, a first bracket, a rail guide, and a first protective film. The first sliding member is coupled to the wafer stage. The second sliding member is coupled to an edge of the table body, in which the first sliding member is coupled to a track of the second sliding member. The first bracket fixes the first cable, the first bracket being coupled to a roller structure, in which the roller structure includes a body and a wheel coupled to the body. The rail guide confines a movement of the wheel of the roller structure. The first protective film is adhered to a surface of the rail guide, in which the roller structure is moveable along the first protective film on the surface of the rail guide.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Hua Wang, Chueh-Chi Kuo, Kuei-Lin Ho, Zong-You Yang, Cheng-Wei Sun, Wei-Yuan Chen, Cheng-Chieh Chen, Heng-Hsin Liu, Li-Jui Chen