Patents by Inventor Kuei-An LIN
Kuei-An LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230400784Abstract: A lithography system includes a table body, a wafer stage, a first sliding member, a second sliding member, a first cable, a first bracket, a rail guide, and a first protective film. The first sliding member is coupled to the wafer stage. The second sliding member is coupled to an edge of the table body, in which the first sliding member is coupled to a track of the second sliding member. The first bracket fixes the first cable, the first bracket being coupled to a roller structure, in which the roller structure includes a body and a wheel coupled to the body. The rail guide confines a movement of the wheel of the roller structure. The first protective film is adhered to a surface of the rail guide, in which the roller structure is moveable along the first protective film on the surface of the rail guide.Type: ApplicationFiled: July 28, 2023Publication date: December 14, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shao-Hua WANG, Chueh-Chi KUO, Kuei-Lin HO, Zong-You YANG, Cheng-Wei SUN, Wei-Yuan CHEN, Cheng-Chieh CHEN, Heng-Hsin LIU, Li-Jui CHEN
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Publication number: 20230395683Abstract: A post-deposition treatment can be applied to an atomic layer deposition (ALD)-deposited film to seal one or more seams at the surface. The seam-top treatment can physically merge the two sides of the seam, so that the surface behaves as a continuous material to allow etching at a substantially uniform rate across the surface of the film. The seam-top treatment can be used to merge seams in ALD-deposited films within semiconductor structures, such as gate-all-around field effect transistors (GAAFETs).Type: ApplicationFiled: June 6, 2022Publication date: December 7, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuei-Lin CHAN, Fu-Ting YEN, Yu-Yun PENG, Keng-Chu LIN
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Patent number: 11832418Abstract: A liquid cooling head includes a chassis, an inlet channel, a thermally-conducting structure, a liquid gathering structure, a drain channel and a pump set. The chassis includes a lower chamber and an upper chamber communicated with the lower chamber through a connection opening. The inlet channel is disposed on one side of the chassis, and communicated with the upper chamber for radiating the heat of the working fluid away. The thermally-conducting structure is disposed in the lower chamber for gathering the working fluid passed through the thermally-conducting structure. The drain channel is disposed on one side of the chassis to be communicated with the lower chamber. The pump set for pushing the working fluid in the lower chamber to discharge the working fluid outwards from the drain channel.Type: GrantFiled: March 26, 2021Date of Patent: November 28, 2023Assignee: AURAS TECHNOLOGY CO., LTD.Inventors: Chien-Yu Chen, Tian-Li Ye, Yu Chen, Jen-Hao Lin, Chien-An Chen, Yun-Kuei Lin
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Publication number: 20230373441Abstract: A heating sticker includes a protective layer, a thermogenic layer, an electrode layer, a cover layer and an adhesive layer, which are superposed in order. The thermogenic layer is a conductive film with transparent carbon nanobuds and defined with a heating area and a non-heating area. The heating area is disposed with insulative grooves. The non-heating area is distributed with micro blocks which are arranged insulatively. The electrode layer has a conductive wire and a ground wire. The conductive wire surrounds the heating area in a non-closed shape. The ground wire is located between the front end and the rear end of the conductive wire and connected to a periphery of the heating area. Conductivity of each of the conductive wire and the ground wire is higher than conductivity of the thermogenic layer. An outer surface of the cover layer is a modified surface which is treated with plasma.Type: ApplicationFiled: May 19, 2022Publication date: November 23, 2023Applicant: Young Fast Optoelectronics Co., Ltd.Inventors: Chih-Chiang Pai, Meng-Kuei Lin, Chun-Hao Huang, Jung-Han Liu, Chih-Jung Tsui
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Publication number: 20230367062Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
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Patent number: 11809000Abstract: A photonic integrated circuit includes a substrate, an interconnection layer, and a plurality of silicon waveguides. The interconnection layer is over the substrate. The interconnection layer includes a seal ring structure and an interconnection structure surrounded by the seal ring structure. The seal ring structure has at least one recess from a top view. The recess concaves towards the interconnection structure. The silicon waveguides are embedded in the substrate.Type: GrantFiled: March 19, 2021Date of Patent: November 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Yuan Yu, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Ming Weng, Hua-Kuei Lin, Che-Hsiang Hsu
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Publication number: 20230326988Abstract: A device includes at least one semiconductor unit which includes a first source/drain portion, a second source/drain portion, at least one nanosheet segment which is disposed to interconnect the first and second source/drain portions, a gate portion disposed around the at least one nanosheet segment, and a first inner spacer portion and a second inner spacer portion which are disposed to separate the gate portion from the first and second source/drain portions, respectively. Each of the first and second inner spacer portions has a carbon-rich region which confronts the gate portion.Type: ApplicationFiled: April 8, 2022Publication date: October 12, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu-Ting YEN, Kuei-Lin CHAN, Yu-Yun PENG
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Patent number: 11782350Abstract: A lithography system includes a table body, a wafer stage, a first sliding member, a second sliding member, a first cable, a first bracket, a rail guide, and a first protective film. The first sliding member is coupled to the wafer stage. The second sliding member is coupled to an edge of the table body, in which the first sliding member is coupled to a track of the second sliding member. The first bracket fixes the first cable, the first bracket being coupled to a roller structure, in which the roller structure includes a body and a wheel coupled to the body. The rail guide confines a movement of the wheel of the roller structure. The first protective film is adhered to a surface of the rail guide, in which the roller structure is moveable along the first protective film on the surface of the rail guide.Type: GrantFiled: August 9, 2022Date of Patent: October 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shao-Hua Wang, Chueh-Chi Kuo, Kuei-Lin Ho, Zong-You Yang, Cheng-Wei Sun, Wei-Yuan Chen, Cheng-Chieh Chen, Heng-Hsin Liu, Li-Jui Chen
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Patent number: 11768338Abstract: An optical interconnect structure including a base substrate, an optical waveguide, a first reflector, a second reflector, a dielectric layer, a first lens, and a second lens is provided. The optical waveguide is embedded in the base substrate. The optical waveguide includes a first end portion and a second end portion opposite to the first end portion. The first reflector is disposed between the base substrate and the first end portion of the optical waveguide. The second reflector is disposed between the base substrate and the second end portion of the optical waveguide. The dielectric layer covers the base substrate and the optical waveguide. The first lens is disposed on the dielectric layer and located above the first end portion of the optical waveguide. The second lens is disposed on the dielectric layer and located above the second end portion of the optical waveguide.Type: GrantFiled: May 27, 2021Date of Patent: September 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Yu-Hsiang Hu, Chewn-Pu Jou, Feng-Wei Kuo
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Patent number: 11758692Abstract: A heat dissipation module is provided and includes a cold plate having a housing, and a frame body disposed on the housing and having two sidewalls and at least one first rib, where the two sidewalls are positioned at two sides of the housing, respectively, and the first rib is used to provide a deformation resistance so that the heat dissipation module will not be seriously deformed when secured.Type: GrantFiled: March 9, 2021Date of Patent: September 12, 2023Assignee: AURAS TECHNOLOGY CO., LTD.Inventors: Chien-An Chen, Chien-Yu Chen, Wei-Hao Chen, Bo-Zhang Chen, Chun-Chi Lai, Yun-Kuei Lin
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Patent number: 11754780Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.Type: GrantFiled: May 13, 2021Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
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Publication number: 20230280558Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: ApplicationFiled: May 5, 2023Publication date: September 7, 2023Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Publication number: 20230245967Abstract: A manufacturing method of a semiconductor package includes the following steps. A supporting layer is formed over a redistribution structure. A first planarization process is performed over the supporting layer. A lower dielectric layer is formed over the supporting layer, wherein the lower dielectric layer includes a concave exposing a device mounting region of the supporting layer. A first sacrificial layer is formed over the supporting layer, wherein the sacrificial layer filling the concave. A second planarization process is performed over the lower dielectric layer and the first sacrificial layer. A transition waveguide provided over the lower dielectric layer. The first sacrificial layer is removed. A semiconductor device is mounted over the device mounting region, wherein the semiconductor device includes a device waveguide is optically coupled to the transition waveguide.Type: ApplicationFiled: March 27, 2023Publication date: August 3, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
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Publication number: 20230236372Abstract: Photonic devices and methods of manufacture are provided. In embodiments a fill material and/or a secondary waveguide are utilized in order to protect other internal structures such as grating couplers from the rigors of subsequent processing steps. Through the use of these structures at the appropriate times during the manufacturing process, damage and debris that would otherwise interfere with the manufacturing process of the device or operation of the device can be avoided.Type: ApplicationFiled: March 27, 2023Publication date: July 27, 2023Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Chih-Hsuan Tai, Hua-Kuei Lin, Tsung-Yuan Yu, Min-Hsiang Hsu
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Patent number: 11686908Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: GrantFiled: January 3, 2022Date of Patent: June 27, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Publication number: 20230152542Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: ApplicationFiled: January 3, 2022Publication date: May 18, 2023Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 11640935Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.Type: GrantFiled: July 16, 2021Date of Patent: May 2, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
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Publication number: 20230122849Abstract: The present invention relates to a method of treating moderate or severe symptoms of COVID-19 using a plant composition. The plant composition comprises Prepared Monkshood Daughter Root (Aconitum carmichaelii), Fragrant Solomonseal Rhizome (Polygonatum odoratum), Indian Bread (Poria cocos), Pinellia tuber (Pinellia ternata), Oriental Wormwood Herb (Artemisia scoparia), Scutellaria Root (Scutellaria baicalensis), Mongolian Snakegourd Fruit (Trichosanthes kirilowii), Magnolia Bark (Magnolia officinalis), Heartleaf Houttuynia Herb (Houttuynia cordata), and Baked Licorice Root and Rhizome (Glycyrrhiza glabra), which is used as a traditional Chinese medicine composition.Type: ApplicationFiled: October 19, 2022Publication date: April 20, 2023Inventors: YI-CHANG SU, WEN-HUI CHIOU, YUH-CHIANG SHEN, WEN-CHI WEI, KENG-CHANG TSAI, CHIA-CHING LIAO, YU-HWEI TSENG, CHUN-TANG CHIOU, YU-CHI LIN, LI-HSIANG WANG, CHIEN-HSIEN HUANG, CHIA-MO LIN, CHI-KUEI LIN, YI-CHIA HUANG, CHIEN-JUNG LIN, JUI-SHAN LIN, YA-SUNG YANG, CHUN-HSIANG CHIU, SHUN-PING CHENG, HSIEN-HWA KUO, WU-PU LIN, CHEN-SHIEN LIN, BO-CHENG LAI, YUAN-NIAN HSU, TSUNG-LUNG TSAI, WEI-CHEN HSU, TIENG-SIONG FONG, YI-WEN HUANG, CHIA-I TSAI, YA-CHEN YANG, MING-CHE TSAI, MING-HUEI CHENG, SHIH-WEI HUANG
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Publication number: 20230102094Abstract: An image sensor includes a plurality of groups of autofocus sensor units. Each of the groups of autofocus sensor units includes a plurality of sensing portions, a color filter layer disposed on the sensing portions, and a plurality of micro-lenses disposed on the color filter layer and correspondingly above the plurality of sensing portions. The image sensor includes a top film disposed conformally on the plurality of micro-lenses. A joint seam between the micro-lenses within one of the groups of autofocus sensor units has a first depth. A gap between the micro-lenses of the plurality of groups of autofocus sensor units has a second depth. The second depth is larger than the first depth.Type: ApplicationFiled: December 6, 2022Publication date: March 30, 2023Inventors: Kuei-An LIN, Chi-Han LIN
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Patent number: 11614592Abstract: Photonic devices and methods of manufacture are provided. In embodiments a fill material and/or a secondary waveguide are utilized in order to protect other internal structures such as grating couplers from the rigors of subsequent processing steps. Through the use of these structures at the appropriate times during the manufacturing process, damage and debris that would otherwise interfere with the manufacturing process of the device or operation of the device can be avoided.Type: GrantFiled: July 16, 2020Date of Patent: March 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Chih-Hsuan Tai, Hua-Kuei Lin, Tsung-Yuan Yu, Min-Hsiang Hsu