Patents by Inventor Kuei-Wei Huang

Kuei-Wei Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170345794
    Abstract: A structure includes a first package and a second package. The second package is coupled to the first package by one or more connectors. Epoxy flux residue is disposed around the connectors and in contact with the connectors. A method includes providing a first package having first connector pads and providing a second package having corresponding second connector pads. Solder paste is printed on each of the first connector pads. Epoxy flux is printed on each of the solder paste. The first and second connector pads are aligned and the packages are pressed together. The solder paste is reflowed to connect the first connector pads to the second connector pads while leaving an epoxy flux residue around each of the connections.
    Type: Application
    Filed: August 4, 2016
    Publication date: November 30, 2017
    Inventors: Chen-Hua Yu, Wei-Yu Chen, Kuei-Wei Huang, Hsiu-Jen Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu, Hsuan-Ting Kuo
  • Patent number: 9799631
    Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: October 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 9786622
    Abstract: A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The distance between the conductive pillar and the conductive trace is less than or equal to about 16 ?m.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: October 10, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Da Cheng, Chih-Wei Lin, Kuei-Wei Huang, Yu-Peng Tsai, Chun-Cheng Lin, Chung-Shi Liu
  • Publication number: 20170179083
    Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 22, 2017
    Inventors: Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 9673182
    Abstract: A method of forming a package on package (PoP) structure includes forming a first die package, and bonding an external connector of a second die package to a solder paste layer of the first die package. The forming the first die package includes forming a contact pad over a substrate, attaching a metal ball with a convex surface to the contact pad, and applying a solder paste layer over a distal end of the metal ball and leaving at least a portion of the metal ball without solder paste. The forming the first die package also includes attaching a semiconductor die to the substrate, and forming a molding compound between the semiconductor die and the metal ball, where the solder paste layer has a first portion extending above an upper surface of the molding compound and a second portion extending below the upper surface of the molding compound.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Wei-Yu Chen, Meng-Tse Chen, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9666572
    Abstract: A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lin, Ming-Da Cheng, Meng-Tse Chen, Wen-Hsiung Lu, Kuei-Wei Huang, Chung-Shi Liu
  • Patent number: 9589861
    Abstract: An embodiment method for forming a semiconductor device package comprises bonding a first die to a package substrate and forming a molding compound over the package substrate and around the first die. A surface of the first die opposing the package substrate is exposed after forming the molding compound. The method further comprises bonding a plurality of second dies to the surface of the first die opposing the package substrate after forming the molding compound.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: March 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chun-Cheng Lin, Kuei-Wei Huang, Yu-Feng Chen, Chen-Shien Chen
  • Patent number: 9583464
    Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 9543185
    Abstract: Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hung Lin, Kuei-Wei Huang, Chih-Wei Lin, Chun-Cheng Lin, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20160351554
    Abstract: A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound.
    Type: Application
    Filed: August 9, 2016
    Publication date: December 1, 2016
    Inventors: Kuei-Wei Huang, Chih-Wei Lin, Hsiu-Jen Lin, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20160343698
    Abstract: A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.
    Type: Application
    Filed: August 4, 2016
    Publication date: November 24, 2016
    Inventors: Meng-Tse Chen, Kuei-Wei Huang, Tsai-Tsung Tsai, Ai-Tee Ang, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20160343692
    Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
    Type: Application
    Filed: August 8, 2016
    Publication date: November 24, 2016
    Inventors: Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin, Ming-Da Cheng
  • Publication number: 20160322339
    Abstract: A method of forming a package on package (PoP) structure includes forming a first die package, and bonding an external connector of a second die package to a solder paste layer of the first die package. The forming the first die package includes forming a contact pad over a substrate, attaching a metal ball with a convex surface to the contact pad, and applying a solder paste layer over a distal end of the metal ball and leaving at least a portion of the metal ball without solder paste. The forming the first die package also includes attaching a semiconductor die to the substrate, and forming a molding compound between the semiconductor die and the metal ball, where the solder paste layer has a first portion extending above an upper surface of the molding compound and a second portion extending below the upper surface of the molding compound.
    Type: Application
    Filed: July 7, 2016
    Publication date: November 3, 2016
    Inventors: Kuei-Wei Huang, Wei-Yu Chen, Meng-Tse Chen, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20160307815
    Abstract: An embodiment method for forming a semiconductor device package comprises bonding a first die to a package substrate and forming a molding compound over the package substrate and around the first die. A surface of the first die opposing the package substrate is exposed after forming the molding compound. The method further comprises bonding a plurality of second dies to the surface of the first die opposing the package substrate after forming the molding compound.
    Type: Application
    Filed: June 23, 2016
    Publication date: October 20, 2016
    Inventors: Yu-Chih Huang, Chun-Cheng Lin, Kuei-Wei Huang, Yu-Feng Chen, Chen-Shien Chen
  • Publication number: 20160293588
    Abstract: A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.
    Type: Application
    Filed: June 20, 2016
    Publication date: October 6, 2016
    Inventors: Chih-Wei Lin, Ming-Da Cheng, Meng-Tse Chen, Wen-Hsiung Lu, Kuei-Wei Huang, Chung-Shi Liu
  • Publication number: 20160247790
    Abstract: A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package.
    Type: Application
    Filed: May 2, 2016
    Publication date: August 25, 2016
    Inventors: Kuei-Wei Huang, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9418971
    Abstract: A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Kuei-Wei Huang, Tsai-Tsung Tsai, Ai-Tee Ang, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9412723
    Abstract: A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Chih-Wei Lin, Hsiu-Jen Lin, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9412689
    Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 9397062
    Abstract: The described embodiments of mechanisms of forming a die package and package on package (PoP) structure involve forming a solder paste layer over metal balls of external connectors of a die package. The solder paste layer protects the metal balls from oxidation. In addition, the solder paste layer enables solder to solder bonding with another die package. Further, the solder paste layer moves an intermetallic compound (IMC) layer formed between the solder paste layer and the metal balls below a surface of a molding compound of the die package. Having the IMC layer below the surface strengthens the bonding structure between the two die packages.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: July 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Wei-Yu Chen, Meng-Tse Chen, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu