Patents by Inventor Kuei-Wei Huang

Kuei-Wei Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9379032
    Abstract: An embodiment method for forming a semiconductor device package comprises bonding a first die to a package substrate and forming a molding compound over the package substrate and around the first die. A surface of the first die opposing the package substrate is exposed after forming the molding compound. The method further comprises bonding a plurality of second dies to the surface of the first die opposing the package substrate after forming the molding compound.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chun-Cheng Lin, Kuei-Wei Huang, Yu-Feng Chen, Chen-Shien Chen
  • Patent number: 9373610
    Abstract: A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lin, Ming-Da Cheng, Meng-Tse Chen, Wen-Hsiung Lu, Kuei-Wei Huang, Chung-Shi Liu
  • Patent number: 9343386
    Abstract: A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20160079135
    Abstract: An embodiment method for forming a semiconductor device package comprises bonding a first die to a package substrate and forming a molding compound over the package substrate and around the first die. A surface of the first die opposing the package substrate is exposed after forming the molding compound. The method further comprises bonding a plurality of second dies to the surface of the first die opposing the package substrate after forming the molding compound.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 17, 2016
    Inventors: Yu-Chih Huang, Chun-Cheng Lin, Kuei-Wei Huang, Yu-Feng Chen, Chen-Shien Chen
  • Patent number: 9263412
    Abstract: An embodiment is a method including forming a first package and a second package. The first package includes packaging a first die, forming a plurality of solder balls on the first die, and coating the plurality of solder balls with an epoxy flux. The second package includes forming a first electrical connector, attaching a second die adjacent the first electrical connector, forming a interconnect structure over the first die and the first electrical connector, the interconnect structure being a frontside of the second package, forming a second electrical connector over the interconnect structure, and the second electrical connector being coupled to both the first die and the first electrical connector. The method further includes bonding the first package to the backside of the second package with the plurality of solder balls forming a plurality of solder joints, each of the plurality of solder joints being surrounded by the epoxy flux.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu, Wei-Yu Chen, Hsiu-Jen Lin, Kuei-Wei Huang
  • Patent number: 9218999
    Abstract: Packaging process tools and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure including a frame. The frame includes a plurality of apertures adapted to retain a plurality of integrated circuit dies therein. The frame includes at least one hollow region.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: December 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Ming-Da Cheng, Wei-Hung Lin, Kuei-Wei Huang, Chih-Wei Lin, Chun-Cheng Lin, Chung-Shi Liu
  • Publication number: 20150348957
    Abstract: A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.
    Type: Application
    Filed: August 13, 2015
    Publication date: December 3, 2015
    Inventors: Chih-Wei Lin, Ming-Da Cheng, Meng-Tse Chen, Wen-Hsiung Lu, Kuei-Wei Huang, Chung-Shi Liu
  • Patent number: 9117816
    Abstract: A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: August 25, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lin, Ming-Da Cheng, Meng-Tse Chen, Wen-Hsiung Lu, Kuei-Wei Huang, Chung-Shi Liu
  • Patent number: 9082636
    Abstract: Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: July 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lin, Kuei-Wei Huang, Yu-Peng Tsai, Chun-Cheng Lin, Meng-Tse Chen, Chen-Hua Yu, Mirng-Ji Lii, Chung-Shi Liu, Bor-Ping Jang, Hsiu-Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Wei-Hung Lin
  • Patent number: 9073158
    Abstract: A method includes dispensing an underfill between a first package component and a second package component, wherein the first package component is placed on a lower jig, and the second package component is over and bonded to the first package component. A through-opening is in the lower jig and under the first package component. The underfill is cured, wherein during the step of curing the underfill, a force is applied to flatten the first package component. The force is applied by performing an action selected from the group consisting of vacuuming and air blowing through the through-opening.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: July 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chun-Cheng Lin, Kuei-Wei Huang, Yu-Peng Tsai, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20150187723
    Abstract: The described embodiments of mechanisms of forming a die package and package on package (PoP) structure involve forming a solder paste layer over metal balls of external connectors of a die package. The solder paste layer protects the metal balls from oxidation. In addition, the solder paste layer enables solder to solder bonding with another die package. Further, the solder paste layer moves an intermetallic compound (IMC) layer formed between the solder paste layer and the metal balls below a surface of a molding compound of the die package. Having the IMC layer below the surface strengthens the bonding structure between the two die packages.
    Type: Application
    Filed: December 30, 2014
    Publication date: July 2, 2015
    Inventors: Kuei-Wei Huang, Wei-Yu Chen, Meng-Tse Chen, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20150179624
    Abstract: A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.
    Type: Application
    Filed: March 4, 2015
    Publication date: June 25, 2015
    Inventors: Chih-Wei Lin, Ming-Da Cheng, Meng-Tse Chen, Wen-Hsiung Lu, Kuei-Wei Huang, Chung-Shi Liu
  • Publication number: 20150171051
    Abstract: Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a tool for processing semiconductor devices includes a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 18, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Hsiu-Jen Lin, Ai-Tee Ang, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9059148
    Abstract: A system and method for forming contacts is provided. An embodiment comprises forming the contacts on a substrate and then coining the contacts by physically shaping them using, e.g., a molding chamber. The physical shaping of the contacts may be performed using a patterned portion of the molding chamber or else by placing a patterned stencil around the contacts prior before a force is applied to physically reshape the contacts. The contacts may be reshaped into a cylindrical, oval, cuboid, or rectangular shape, for example.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: June 16, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Wei-Hung Lin, Kuei-Wei Huang, Chih-Wei Lin, Chih Chun Chiu, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20150091193
    Abstract: A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.
    Type: Application
    Filed: October 2, 2013
    Publication date: April 2, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Wei-Hung Lin, Kuei-Wei Huang, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 8975741
    Abstract: A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lin, Ming-Da Cheng, Meng-Tse Chen, Wen-Hsiung Lu, Kuei-Wei Huang, Chung-Shi Liu
  • Publication number: 20150044819
    Abstract: Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.
    Type: Application
    Filed: October 24, 2014
    Publication date: February 12, 2015
    Inventors: Chih-Wei Lin, Kuei-Wei Huang, Yu-Peng Tsai, Chun-Cheng Lin, Meng-Tse Chen, Chen-Hua Yu, Mirng-Ji Lii, Chung-Shi Liu, Bor-Ping Jang, Hsiu-Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Wei-Hung Lin
  • Publication number: 20150008581
    Abstract: A method of packaging includes placing a package component over a release film, wherein solder regions on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder regions remain in physical contact with the release film.
    Type: Application
    Filed: September 23, 2014
    Publication date: January 8, 2015
    Inventors: Meng-Tse Chen, Wei-Hung Lin, Sheng-Yu Wu, Bor-Ping Jang, Ming-Da Cheng, Chung-Shi Liu, Hsiu-Jen Lin, Wen-Hsiung Lu, Chih-Wei Lin, Yu-Peng Tsai, Kuei-Wei Huang, Chun-Cheng Lin
  • Patent number: 8927391
    Abstract: A method of packaging includes placing a package component over a release film, wherein solder balls on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder balls remain in physical contact with the release film.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Wei-Hung Lin, Sheng-Yu Wu, Chun-Cheng Lin, Kuei-Wei Huang, Yu-Peng Tsai, Chih-Wei Lin, Wen-Hsiung Lu, Hsiu-Jen Lin, Bor-Ping Jang, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 8928134
    Abstract: The described embodiments of mechanisms of forming a die package and package on package (PoP) structure involve forming a solder paste layer over metal balls of external connectors of a die package. The solder paste layer protects the metal balls from oxidation. In addition, the solder paste layer enables solder to solder bonding with another die package. Further, the solder paste layer moves an intermetallic compound (IMC) layer formed between the solder paste layer and the metal balls below a surface of a molding compound of the die package. Having the IMC layer below the surface strengthens the bonding structure between the two die packages.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Wei-Yu Chen, Meng-Tse Chen, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu