Abstract: A method is provided for forming an improved contact opening of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Planarization of the semiconductor structure is maximized and misalignment of contact openings is tolerated by first forming a conductive structure over a portion of a first body. A thin dielectric layer is formed at least partially over the conductive structure. A thick film, having a high etch selectivity to the thin dielectric layer, is formed over the dielectric layer. The thick film is patterned and etched to form a stack substantially over the conductive structure. An insulation layer is formed over the thin dielectric layer and the stack wherein the stack has a relatively high etch selectivity to the insulation layer. The insulation layer is etched back to expose an upper surface of the stack.

Abstract: A method is provided for forming an improved planar structure of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide is grown across the integrated circuit patterned and etched to form an opening with substantially vertical sidewalls exposing a portion of an upper surface of a substrate underlying the field oxide where an active area will be formed. A gate electrode comprising a polysilicon gate electrode and a gate oxide are formed over the exposed portion of the substrate. The polysilicon gate has a height at its upper surface above the substrate at or above the height of the upper surface of the field oxide. The gate electrode preferably also comprises a silicide above the polysilicon and an oxide capping layer above the silicide. LDD regions are formed in the substrate adjacent the gate electrode and sidewall spacers are formed along the sides of the gate electrode including the silicide and the capping layer.

Abstract: A method for forming a semiconductor device having air regions, the method comprises providing a base, forming a pattern of metal leads, depositing a layer of oxide over the metal leads, forming a layer of nitride over said layer of oxide, opening and etching a trench down to the base layer of material, and depositing and planarizing a dielectric layer. An alternate approach teaches the deposition of a layer of SOG over the layer of oxide that has been deposited over the metal leads, planarizing this layer of SOG down to the top of the metal leads, depositing a layer of PECVD oxide, patterning and etching this layer of PECVD oxide thereby creating openings that are in between the metal leads. The SOG that is between the metal leads can be removed thereby creating air gaps as the Intra-level dielectric for the metal leads.

Abstract: A method for forming a semiconductor device having air regions, the method comprises providing a base, forming a pattern of metal leads, depositing a layer of oxide over the metal leads, forming a layer of nitride over said layer of oxide, opening and etching a trench down to the base layer of material, and depositing and planarizing a dielectric layer. An alternate approach teaches the deposition of a layer of SOG over the layer of oxide that has been deposited over the metal leads, planarizing this layer of SOG down to the top of the metal leads, depositing a layer of PECVD oxide, patterning and etching this layer of PECVD oxide thereby creating openings that are in between the metal leads. The SOG that is between the metal leads can be removed thereby creating air gaps as the intra-level dielectric for the metal leads.

Abstract: A method is provided for forming an improved contact opening of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Planarization of the semiconductor structure is maximized and misalignment of contact openings is tolerated by first forming a conductive structure over a portion of a first body. A thin dielectric layer is formed at least partially over the conductive structure. A thick film, having a high etch selectivity to the thin dielectric layer, is formed over the dielectric layer. The thick film is patterned and etched to form a stack substantially over the conductive structure. An insulation layer is formed over the thin dielectric layer and the stack wherein the stack has a relatively high etch selectivity to the insulation layer. The insulation layer is etched back to expose an upper surface of the stack.

Abstract: A method is provided for forming an improved contact opening of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Planarization of the semiconductor structure is maximized and misalignment of contact openings is tolerated by first forming a conductive structure over a portion of a first body. A thin dielectric layer is formed at least partially over the conductive structure. A thick film, having a high etch selectivity to the thin dielectric layer, is formed over the dielectric layer. The thick film is patterned and etched to form a stack substantially over the conductive structure. An insulation layer is formed over the thin dielectric layer and the stack wherein the stack has a relatively high etch selectivity to the insulation layer. The insulation layer is etched back to expose an upper surface of the stack.

Abstract: A method is provided to form a split-gate flash memory not susceptible to inadvertent reverse tunneling during programming. This is accomplished by forming a silicon nitride spacer on the negatively tapered walls of the floating gate of the cell which serves as a barrier to reverse tunneling. The negatively tapered walls, in contrast to vertical walls, is disclosed to provide a geometry better suited for forming thicker spacers around the floating gate, which in turn serve to act as a more robust barrier to reverse tunneling. Furthermore, it is shown that the method requires fewer steps than practiced in prior art.

Abstract: A method is achieved for preventing oxide loss on the top corners of the isolation trenches and minimizing parasitic current leakage of the active devices on the substrate. The method consists of forming shallow trenches having either stepped or tapered walls in a silicon substrate using a pad oxide and silicon nitride mask. The dielectric material used to fill the trenches is then etched to form nitride spacers, which protect the top corners of the trench walls from subsequent etching but are removed prior to cleaning of the pad and forming of gate oxide around the trenches.

Abstract: A method is provided to form a split-gate flash memory not susceptible to inadvertent reverse tunneling during programming. This is accomplished by forming a silicon nitride spacer on the negatively tapered walls of the floating gate of the cell which serves as a barrier to reverse tunneling. The negatively tapered walls, in contrast to vertical walls, is disclosed to provide a geometry better suited for forming thicker spacers around the floating gate, which in turn serve to act as a more robust barrier to reverse tunneling. Furthermore, it is shown that the method requires fewer steps than practiced in prior art.

Abstract: A method is provided for forming planar multilevel metallization of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Multilevel metallization is achieved through a planar process at each layer to allow for minimum widths of lines and vias and minimal lateral spacing between lines. Conductive lines and contacts are formed before planarization to further achieve good step coverage. A first metallization layer is formed by depositing aluminum over the integrated circuit, patterning and etching to form metal interconnect lines. Regions of planar insulating material are then formed between the metal lines. Another layer of aluminum is deposited and etched to form metal vias over selected portions of the metal lines. This layer of aluminum is patterned with a reverse pattern of that used to pattern the metal lines. Again, regions of planar insulating material are formed between the metal vias.

Abstract: A method is provided for forming planar multilevel metallization of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Multilevel metallization is achieved through a planar process at each layer to allow for minimum widths of lines and vias and minimal lateral spacing between lines. Conductive lines and contacts are formed before planarization to further achieve good step coverage. A first metallization layer is formed by depositing aluminum over the integrated circuit, patterning and etching to form metal interconnect lines. Regions of planar insulating material are then formed between the metal lines. Another layer of aluminum is deposited and etched to form metal vias over selected portions of the metal lines. This layer of aluminum is patterned with a reverse pattern of that used to pattern the metal lines. Again, regions of planar insulating material are formed between the metal vias.

Abstract: A method to create raised landing pads for gate electrodes. A layer of polysilicon is deposited over the gate electrode after the gate spacers and the gate isolation areas have been formed. The gate electrode contains two layers, that is a bottom layer of poly and a top layer of oxide or SOG. A layer of photo resist is deposited over the polysilicon, a pattern of landing pads is created in the photo resist. The layer of polysilicon is etched in accordance with the pattern in the photo resist thus forming the elevated landing pads. Source and drain areas of the gate electrode can be contacted by metallic contacts that are in interconnects with these landing pads. The top layer of the gate electrode is removed making the gate electrode a recessed electrode. The invention thereby provides an easy method for removing (by CMP) any bridging that might occur (between the gate electrode and the landing pads) during salicidation.

Abstract: A method for forming a semiconductor device having air regions, the method comprises providing a base, forming a pattern of metal leads, depositing a layer of oxide over the metal leads, forming a layer of nitride over said layer of oxide, opening and etching a trench down to the base layer of material, and depositing and planarizing a dielectric layer. An alternate approach teaches the deposition of a layer of SOG over the layer of oxide that has been deposited over the metal leads, planarizing this layer of SOG down to the top of the metal leads, depositing a layer of PECVD oxide, patterning and etching this layer of PECVD oxide thereby creating openings that are in between the metal leads. The SOG that is between the metal leads can be removed thereby creating air gaps as the intra-level dielectric for the metal leads.

Abstract: The cross-sectional area of a thin-film transistor (TFT) is decreased in order to minimize bitline to supply leakage of the TFT. This is accomplished by utilizing a spacer etch process to manufacture a TFT having a very narrow and thin channel in a controllable manner. The spacer dimensions of the TFT may be adjusted by simply modifying the thicknesses of the poly gate and the channel poly. The channel thickness is limited by the thickness of the deposited channel polysilicon which may be as thin as approximately 300 .ANG. to 500 .ANG., and the channel width of the TFT corresponds to the height of the spacer etched along the polysilicon gate of the device which may be as small as approximately 0.15 to 0.25 .mu.m.

Abstract: A method is provided for forming an improved planar structure of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide is grown across the integrated circuit patterned and etched to form an opening with substantially vertical sidewalls exposing a portion of an upper surface of a substrate underlying the field oxide where an active area will be formed. A gate electrode comprising a polysilicon gate electrode and a gate oxide are formed over the exposed portion of the substrate. The polysilicon gate has a height at its upper surface above the substrate at or above the height of the upper surface of the field oxide. The gate electrode preferably also comprises a silicide above the polysilicon and an oxide capping layer above the silicide. LDD regions are formed in the substrate adjacent the gate electrode and sidewall spacers are formed along the sides of the gate electrode including the silicide and the capping layer.

Abstract: The cross-sectional area of a thin-film transistor (TFT) is decreased in order to minimize bitline to supply leakage of the TFT. This is accomplished by utilizing a spacer etch process to manufacture a TFT having a very narrow and thin channel in a controllable manner. The spacer dimensions of the TFT may be adjusted by simply modifying the thicknesses of the poly gate and the channel poly. The channel thickness is limited by the thickness of the deposited channel polysilicon which may be as thin as approximately 300 .ANG. to 500 .ANG., and the channel width of the TFT corresponds to the height of the spacer etched along the polysilicon gate of the device which may be as small as approximately 0.15 to 0.25 .mu.m.

Abstract: A method for planarization of an integrated circuit. After a first conducting layer is deposited and patterned, a first insulating layer is deposited over the device. A planarizing layer is then deposited over the integrated circuit and etched back. Portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the device. A second insulating layer is then deposited over the integrated circuit, followed by a third insulating layer. A contact via is formed through the layers to expose a portion of the first conducting layer. A second conducting layer can now be deposited and patterned on the device to make electrical contact with the first conducting layer.

Abstract: A method for forming contact vias in a integrated circuit which do not have planarizing material nearby. After a first insulating layer is deposited over the integrated circuit, a planarizing layer is deposited over the first insulating layer. The planarizing layer is etched back and portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the integrated circuit. A first masking layer is then formed over the surface of the integrated circuit. The openings created in the first masking layer have a size which is greater than the size of the contact vias to be formed. The first insulating layer is partially etched into so that portions of the planarizing layer near the locations of the contact vias are removed. The first masking layer is then removed, and a second insulating layer is deposited over the integrated circuit.

Abstract: A method for forming contact vias in a integrated circuit which do not have planarizing material nearby. After a first insulating layer is deposited over the integrated circuit, a planarizing layer is deposited over the first insulating layer. The planarizing layer is etched back and portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the integrated circuit. A first masking layer is then formed over the surface of the integrated circuit. The openings created in the first masking layer have a size which is greater than the size of the contact vias to be formed. The first insulating layer is partially etched into so that portions of the planarizing layer near the locations of the contact vias are removed. The first masking layer is then removed, and a second insulating layer is deposited over the integrated circuit.

Abstract: A method for planarizing an integrated circuit structure having a glass layer overlying an oxide layer of an integrated circuit is presented. The method includes the steps of selectively etching portions of the glass structure that overlie portions of the oxide layer that have higher elevations than other portions of the oxide layer, and then etching the glass layer overall. The etching step includes forming a layer of photoresist over the glass layer, exposing selected areas of the photoresist over the portions of the oxide layer that have higher elevations than other portions of the oxide layer, removing the exposed areas of the photoresist, and etching the glass layer within the removed areas of the photoresist. The mask used in patterning the photoresist can be the same mask, or its negative, that is used in forming the metalization layer over which the oxide and glass layers have been formed.