Abstract: A structure and method is provided for fabricating an integrated circuit having an N-type well and a P-type well, with the upper surfaces of the N-type well and the P-type well coplanar. An insulating layer is formed over the integrated circuit. A first masking layer is formed over the insulating layer to define locations of a first well to be formed. An impurity of a first conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a first region. The first masking layer is removed, and a second masking layer is formed over the insulating layer to define locations of a second well to be formed. An impurity of a second conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a second region. The second masking layer is then removed. The integrated circuit is thermally heated to form the first and second wells in the substrate.

Abstract: An integrated circuit structure is presented that includes a substrate in which integrated circuit elements are constructed, a first interconnection metalization over the substrate interconnecting selected ones of the integrated circuit elements, and an oxide layer over the substrate and the first metal interconnection pattern. A glass layer over the oxide layer is substantially planar between portions that overlie the metalization and portions that do not over lie the metalization.

Abstract: According to the present invention, a thin conductive layer is formed over an underlying structure in an integrated circuit. The underlying structure can be either a semiconductor substrate or an interlevel interconnect signal line. An insulating layer is deposited over the device. The insulating layer is patterned and etched in order to expose a portion of the underlying conductive layer and to define an interconnect signal line. When the signal line locations are etched away, the thin conductive layer acts as an etch stop and protects the underlying structure. A metal refill process can be used to then form interconnects and contacts within the etched interconnect lines. This results in interconnect and contacts having upper surfaces which are substantially coplanar with the upper surface of the insulating layer in which they are formed.