Patents by Inventor Kuen-Long Chang

Kuen-Long Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus of supplying power while maintaining its output power signal and method therefor
    Patent number: 9423814
    Abstract: A power supply apparatus and a method for supplying power are provided. The method includes: providing a first power supply for outputting a first power signal; providing a second power supply for outputting a second power signal; and selectively charging the second power supply by using the first power supply.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: August 23, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Ting Hu, Chun-Hsiung Hung, Wu-Chin Peng, Kuen-Long Chang, Ken-Hui Chen
  • Input pin control
    Patent number: 9417640
    Abstract: An integrated circuit device includes a pad adapted to receive a signal from an external driver. A state register is programmed with a state that indicates a voltage level to set for the pad during initialization of circuitry on the integrated circuit device responsive to the state for the pad. The voltage level may correspond to a logic low level or a logic high level. A voltage holding circuit is coupled to the pad and the state register, and is configured to force the pad to the voltage level in response to an event that causes the initialization.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: August 16, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Chin-Hung Chang, Chao-Hsin Lin
  • MEMORY DEVICE AND OPERATING METHOD OF SAME
    Publication number: 20160232950
    Abstract: A memory device includes a memory array and a logic unit communicatively coupled to the memory array. The memory array includes a plurality of pages for storing array data and a plurality of extra arrays respectively corresponding to the plurality of pages for storing extra data. The logic unit is configured to receive a read instruction, and perform a read operation in a first access mode or in a second access mode. In the first access mode, the logic unit sequentially reads out the array data stored in the plurality of pages. In the second access mode, the logic unit sequentially reads out the array data stored in the plurality of pages and the extra data stored in the plurality of extra arrays.
    Type: Application
    Filed: February 11, 2015
    Publication date: August 11, 2016
    Inventors: Kuen-Long CHANG, Ken-Hui CHEN, Ming-Chih HSIEH
  • Memory device and erasing method thereof
    Patent number: 9400712
    Abstract: An erasing method of a memory device is provided. The memory device includes a memory controller and a memory array having a first memory region and a second memory region. The first memory region and the second memory region share the same well. The erasing method comprising steps of: erasing the first memory region; and selectively programming the second memory region according to an error correction code algorithm.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: July 26, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chin-Hung Chang, Chia-Feng Cheng, Yu-Chen Wang, Ken-Hui Chen, Kuen-Long Chang
  • Memory device and operating method of same
    Patent number: 9396769
    Abstract: A memory device includes a memory array and a logic unit communicatively coupled to the memory array. The memory array includes a plurality of pages for storing array data and a plurality of extra arrays respectively corresponding to the plurality of pages for storing extra data. The logic unit is configured to receive a read instruction, and perform a read operation in a first access mode or in a second access mode. In the first access mode, the logic unit sequentially reads out the array data stored in the plurality of pages. In the second access mode, the logic unit sequentially reads out the array data stored in the plurality of pages and the extra data stored in the plurality of extra arrays.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: July 19, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Ming-Chih Hsieh
  • Method, electronic device and controller for recovering memory array
    Patent number: 9396806
    Abstract: A method, an electronic device and a controller for recovering an array of memory cells are provided. The method comprises the following steps. Whether a recovery control signal is received or not is determined. A retention checking procedure is executed for identifying whether a threshold voltage distribution of at least one bit of the memory cells in high threshold state is shifted or not, if the recovery control signal is received. A retention writing procedure is executed on the memory cells, if the memory cells in high threshold state do not pass the retention checking procedure.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: July 19, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Nai-Ping Kuo, Ken-Hui Chen, Chao-Hsin Lin
  • POWER DROP DETECTOR CIRCUIT AND OPERATING METHOD OF SAME
    Publication number: 20160204772
    Abstract: A power drop detector circuit includes a detect element, for coupling to a first source voltage, for detecting a voltage level of the first source voltage, and a memory element coupled to the detect element and switchable between a first memory state and a second memory state based on the voltage level of the first source voltage.
    Type: Application
    Filed: September 22, 2015
    Publication date: July 14, 2016
    Inventors: Kuan-Ming LU, Chun-Hsiung HUNG, Chun-Yi LEE, Ken-Hui CHEN, Kuen-Long CHANG
  • CHARGE PUMP CIRCUIT AND METHOD OF CONTROLLING SAME
    Publication number: 20160204695
    Abstract: A charge pump circuit includes a plurality of branches coupled in parallel, each branch including a plurality of sub-blocks coupled in series, and each sub-block including a unit pump circuit. The charge pump circuit also includes a plurality of clock transfer circuits coupled to corresponding ones of the plurality of branches for providing clock signals to the corresponding branches. The sub-blocks of different branches are enabled and driven by the clock signals at different times.
    Type: Application
    Filed: June 12, 2015
    Publication date: July 14, 2016
    Inventors: Wu-Chin PENG, Hsing-Yu LIU, Chun-Yi LEE, Ken-Hui CHEN, Kuen-Long CHANG, Chun Hsiung HUNG
  • POWER SOURCE FOR MEMORY CIRCUITRY
    Publication number: 20160203846
    Abstract: An integrated circuit comprises a power supply input pin receiving an off-chip supply voltage having a variable current, an on-chip power source powered by the off-chip supply voltage and providing a regulated current, a memory array, and a set of one or more circuits coupled to the memory array and powered by the regulated current from the on-chip power source. The IC can include control circuitry performing memory operations on the memory array, said control circuitry powered by at least the off-chip supply voltage from the power supply pin.
    Type: Application
    Filed: October 7, 2015
    Publication date: July 14, 2016
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: WU-CHIN PENG, CHUN-YI LEE, KEN-HUI CHEN, KUEN-LONG CHANG, CHUN HSIUNG HUNG
  • POWER SOURCE FOR MEMORY CIRCUITRY
    Publication number: 20160203845
    Abstract: An integrated circuit comprises a power supply input pin for receiving an off-chip supply voltage which can have a variable current, an on-chip power source to be powered by the off-chip supply voltage and which can provide a regulated current, a set of one or more circuits to be powered by at least one of the off-chip supply voltage and the on-chip power source, a configuration memory storing a set of one or more memory settings that indicate whether a circuit of said set of one or more circuits is powered by the on-chip power source, and control circuitry responsive to the at least one memory setting to control whether said circuit of said set of one or more circuits is powered by the on-chip power source.
    Type: Application
    Filed: October 7, 2015
    Publication date: July 14, 2016
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: WU-CHIN PENG, CHUN-YI LEE, KEN-HUI CHEN, KUEN-LONG CHANG, CHUN HSIUNG HUNG
  • DECODE SWITCH AND METHOD FOR CONTROLLING DECODE SWITCH
    Publication number: 20160204697
    Abstract: A decode switch and a method for controlling a decode switch are provided. The decode switch includes a power source providing a first voltage, a source capacitance coupled to the power source, and a target capacitance coupled to the power source. The power source charges the source capacitance to the first voltage. The source capacitance is connected to the target capacitance and the source capacitance charges the target capacitance to a second voltage. The power source charges the target capacitance from the second voltage to the first voltage.
    Type: Application
    Filed: April 22, 2015
    Publication date: July 14, 2016
    Inventors: Yi-Fan Chang, Chun-Yi Lee, Ken-Hui Chen, Kuen-Long Chang, Chun-Hsiung Hung
  • Non-volatile memory device and method for shortened erase operation during testing
    Patent number: 9368220
    Abstract: A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: June 14, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen, Nai-Ping Kuo, Chin-Hung Chang, Chang-Ting Chen
  • DEVICE AND METHOD FOR DETECTING CONTROLLER SIGNAL ERRORS IN FLASH MEMORY
    Publication number: 20160139983
    Abstract: In accordance with the disclosure, there is provided a memory device configured to implement an error detection protocol. The memory device includes a memory array and a first input for receiving a control signal corresponding to a command cycle. The memory device also includes a second input for receiving an access control signal during a command cycle and for receiving an error detection signal during the command cycle, wherein the error detection signal includes information corresponding to the access control signal. The memory device further includes control logic configured to verify the correctness of the access control signal by a comparison with the error detection signal and perform an operation on the memory array during the command cycle when the correctness of the access control signal is verified.
    Type: Application
    Filed: September 11, 2015
    Publication date: May 19, 2016
    Inventors: Kuen Long CHANG, Ken Hui CHEN, Su Chueh LO, Chia-Feng CHENG
  • MONITORING DATA ERROR STATUS IN A MEMORY
    Publication number: 20160117218
    Abstract: A method for outputting data error status of a memory device includes generating a data status indication code indicating error status of a data chunk transmitted by a memory controller, combining the data status indication code with the data chunk to generate an output signal, and outputting the output signal to a data bus pin.
    Type: Application
    Filed: February 3, 2015
    Publication date: April 28, 2016
    Inventors: Kuen Long CHANG, Ken Hui CHEN, Su Chueh LO, Chia-Feng CHENG
  • METHOD AND DEVICE FOR COMMAND PROCESSING
    Publication number: 20160085715
    Abstract: A method for command processing in a memory controller includes receiving a serial input signal including a series of binary digits, capturing the binary digits at ones of odd locations or even locations of the serial input signal to form a first sub-series, capturing the binary digits at other ones of the odd locations or the even locations of the serial input signal to form a second sub-series, comparing the first and second sub-series, and performing a command represented by the first sub-series, if the first and second sub-series are complementary to each other.
    Type: Application
    Filed: February 11, 2015
    Publication date: March 24, 2016
    Inventors: Ken Hui CHEN, Kuen Long CHANG, Yu Chen WANG
  • Programming method, reading method and operating system for memory
    Patent number: 9286158
    Abstract: A programming method, a reading method and an operating system for a memory are provided. The programming method includes the following steps. A data is provided. A parity generation is performed to obtain an error-correcting code (ECC). The memory is programmed to record the data and the error-correcting code. The data is transformed before performing the parity generation, such that a hamming distance between two codes corresponding to two adjacent threshold voltage states in the data to be performed the parity generation is 1.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: March 15, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chien-Hsin Liu, Su-Chueh Lo, Kuen-Long Chang, Ken-Hui Chen, Chun-Hsiung Hung
  • CIRCUIT FOR VOLTAGE DETECTION AND PROTECTION AND OPERATING METHOD THEREOF
    Publication number: 20160064921
    Abstract: A circuit for voltage detection and protection comprises a first block, a first voltage detector, a second block and a second voltage detector. The first block receives a first voltage supply. The first voltage detector detects the first voltage supply and generates a first detecting signal when detecting the first voltage supply level is out of the first operating voltage range. The second block receives a second voltage supply. The second voltage detector detects the second voltage supply and generates a second detecting signal when detecting the second voltage supply level is out of the second operating voltage range. The first block performs a protection operation on the circuit when monitoring at least one of the first and second detecting signals.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 3, 2016
    Inventors: Yu-Meng Chaung, Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen
  • Memory device and read operation method thereof
    Patent number: 9275695
    Abstract: A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: March 1, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chin-Hung Chang, Chia-Jung Chen, Su-Chueh Lo, Ken-Hui Chen, Kuen-Long Chang
  • STABILIZATION OF OUTPUT TIMING DELAY
    Publication number: 20160049925
    Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. Alternatively, the output buffer delay is variable. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and can include a first delay circuit that generates the first timing signal with a first delay, and a second delay circuit that generates the second timing signal with a second delay that correlates with the output buffer delay.
    Type: Application
    Filed: August 13, 2014
    Publication date: February 18, 2016
    Applicant: Macronix International Co., Ltd.
    Inventors: Yu-Meng Chaung, Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen
  • METHOD AND DEVICE FOR MONITORING DATA ERROR STATUS IN A MEMORY
    Publication number: 20160041861
    Abstract: A method for monitoring data error status of a memory device includes generating, by a memory controller, a data status indication code indicating error status of a data chunk transmitted by the memory controller and outputting, by the memory controller, the data status indication code to a user interface.
    Type: Application
    Filed: January 14, 2015
    Publication date: February 11, 2016
    Inventors: Kuen Long CHANG, Ken Hui CHEN, Su Chueh LO, Chia-Feng CHENG