Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, including a plurality of lower electrode pillars that are arranged at intervals; a dielectric layer, at least partially covering a sidewall of each of the lower electrode pillars; a first upper electrode, covering a surface of the dielectric layer; a first support layer, located above the plurality of lower electrode pillars, the dielectric layer, and the first upper electrode, wherein the first support layer at least exposes a peripheral region of a part of the first upper electrode.

Abstract: A semiconductor structure and a manufacturing method are provided. The semiconductor structure includes: a substrate having a bit line extending along a first direction; a semiconductor channel located on the bit line; a semiconductor doping layer located on the side of the bit line, wherein the top surface of the semiconductor doping layer is connected to the semiconductor channel contact; a word line extending in the second direction, encircling part of the semiconductor channel, and the bottom surface of the word line is higher than the top surface of the bit line; a word line dielectric layer located between the word line and the semiconductor channel; an isolation layer located between the word line and the bit line and between the word line and the semiconductor doping layer. The device and method improve the prior weak electrical conductivity between the bit line structure and the active structure.

Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a semiconductor base, a bit line and a word line. The semiconductor base includes a substrate and an isolation structure. The isolation structure is arranged above the substrate and configured to isolate a plurality of active regions from each other. The bit line is arranged in the substrate and connected to the plurality of active regions. The word line is arranged in the isolation structure, intersects with the plurality of active regions and surrounds the plurality of active regions. The substrate is a Silicon-On-Insulator (SOI) substrate.

Abstract: The present application is applicable to the field of semiconductor technology and provides a method for packaging stacking a flip chip, which includes: placing a filling template on a substrate, the filling template being provided with a through hole of a preset pattern; filling a filling material into the through hole of the filling template, and after the filling material being formed on the substrate, removing the filling template; placing a chip with solder balls on the substrate formed with the filling material, such that at least a portion of the solder balls being covered by the filling material; and connecting the chip to the substrate through the solder balls, and curing the filling material with air gaps formed between the at least a portion of the solder balls covered with the filling material.

Abstract: The present disclosure provides a display panel, a method for preparing the same, and a display device. The display panel includes: a display substrate, including a base substrate, a driving transistor embedded on the base substrate, and a first electrode layer located on the base substrate; an encapsulation protection structure located on the display substrate and surrounding a display area of the display substrate; a light emitting layer located on a surface of the first electrode layer away from the base substrate; a second electrode layer located on a surface of the light emitting layer away from the base substrate; and a first encapsulation layer located on a surface of the second electrode layer away from the base substrate.

Abstract: Provided is a manufacturing method of a semiconductor structure, including: providing a substrate; forming a first mask layer having a first mask pattern on the substrate, and etching the substrate by using the first mask layer as a mask to form active regions; forming several discrete bitlines on the active regions; forming a sacrificial layer between adjacent bitlines; forming a second mask layer having a second mask pattern on the sacrificial layer, the first mask pattern and the second mask pattern being complementary to each other; and etching the sacrificial layer by using the second mask layer and the bitlines as masks to form a plurality of contact structures. The embodiment of the present disclosure is beneficial to reducing the manufacturing cost of the semiconductor structure.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a semiconductor body, bit lines and word lines. The semiconductor body includes a substrate and an isolation structure positioned above the substrate and configured to isolate a plurality of active regions, part of each of the active regions being formed from the substrate. The bit lines are positioned in the substrate and are connected to the active regions. The word lines intersect with the active regions and surround the active regions. The substrate is Silicon On Insulator (SOI) substrate.

Abstract: A high-precision analysis method for key thermal safety phenomena in a nuclear reactor based on a particle method is provided. Fine complex geometric modeling is implemented based on a multi-resolution particle method. High-order discretization of control equations is implemented using a high-order particle discretization model. Key thermal-hydraulic, mechanical deformation, chemical reaction, and neutron physics phenomena can be analyzed. An implicit and explicit hybrid solving technique and an asynchronous marching algorithm are employed.

Abstract: The technology of this application relates to a memory management method and apparatus. When garbage collection is performed by using the method, stored information about a first reference cycle is first obtained, where the first reference cycle is a cyclic reference formed by a plurality of objects, and the information about the first reference cycle includes the plurality of objects in the first reference cycle and a reference relationship between the plurality of objects. The method further includes determining that a second reference cycle exists, where information about the second reference cycle matches the information about the first reference cycle, and the information about the second reference cycle includes a plurality of objects in the second reference cycle and a reference relationship between the plurality of objects. The method further includes reclaiming memory occupied by the plurality of objects in the second reference cycle.

Abstract: The utility model discloses a pipe connection mechanism, a refrigeration system having the same, and a refrigeration appliance. The pipe connection mechanism is used for connecting a flexible pipe and a rigid pipe, and includes: a joint pipe and a sleeve sleeving the flexible pipe, wherein the joint pipe has a first pipe part fixedly connected to the rigid pipe, and a second pipe part forward inserted into the flexible pipe and stretching the flexible pipe in an interference manner; and the sleeve backward sleeves the second pipe part and the sleeve and the second pipe part clamp and fix the flexible pipe together. The refrigeration system includes a rigid pipe and a flexible pipe which are fixedly connected in a fit manner through the pipe connection mechanism.

Abstract: This invention relates to a method of increasing the size of particulates in a gas comprising particulates, e.g. a gas that is formed from the combustion of fuels. The method comprises mixing an ionised gas stream with the gas comprising particulates.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing a semiconductor device. Every two first wires of a first conductive layer of the semiconductor device have a common end, and every two second wires of a second conductive layer of the semiconductor device have a common end.

Abstract: A semiconductor structure includes a base and conductive channel structure which includes first and second conductive channel layers and conductive buffer layer. The first conductive channel layer includes a first conductive channel, first and second doped regions on both sides of the first conductive channel; the second conductive channel layer includes a second conductive channel and third and fourth doped regions on both sides of the second conductive channel; the conductive buffer layer reduces electrical interference between the first and third doped regions. The semiconductor structure further includes a first wire layer disposed on the base extending in a direction and in contact with the second doped region; a second wire layer extending in another direction and in contact with the first and third doped regions; and a gate structure disposed around the first and second conductive channels.

Abstract: A method, system, and computer program product are configured to: create a link tracing data structure in response to receiving a request from a user interface (UI), wherein the link tracing data structure includes a synchronization identifier and information about user actions in the UI; handle the request by calling plural microservices; add respective synchronization content for each one of the plural microservices to the link tracing data structure, wherein the respective synchronization content for a respective one of the plural microservices comprises: the synchronization identifier; a respective step identifier that identifies the respective one of the plural microservices; and a respective synchronization message that describes an execution status of the respective one of the plural microservices; store the link tracing data structure; and provide the link tracing data structure to a requesting user.

Abstract: A memory and a method for manufacturing the same are provided. The memory includes a substrate; at least one pair of transistors on a surface of the substrate, in which conductive channels of the transistors extend in a direction perpendicular to the surface of the substrate; storage layers, which each are located, in the direction perpendicular to the surface of the substrate, on a side surface of each of the transistors, the storage layers are interconnected with the conductive channels of the transistors, any one of the storage layers is located between the pair of transistors, and the storage layers are configured to store electric charges and transfer the electric charges between the storage layers and the conductive channels interconnected therewith.

Abstract: The present disclosure relates to a spheroidizing-annealed steel for the ball screw having high strength and resistance to low temperatures, wherein the chemical composition of the steel in mass percentage is: C: 0.40-0.70%, Si: 1.20-1.80%, Mn: 1.00-1.60%, Cr: 0.80-1.20%, S: ?0.025%, P?0.025%, Ni: 0.10-0.60%, Cu: 0.30-0.80%, Mo: 0.10-0.40%, Al?0.05%, Ca?0.0010%, Ti?0.003%, O?0.0010%, As?0.04%, Sn?0.03%, Sb?0.005%, Pb?0.002%, the balance is Fe and unavoidable impurities. In microstructure of the steel, cementite exists in a spheroidized state with a diameter of 0.1-0.5 ?m, preferably 0.3-0.5 ?m, a spheroidizing rate is 95% or more, and the rest is ferrite.

Abstract: A semiconductor structure includes a base and a conductive channel structure, in which the conductive channel structure includes a base and a conductive channel structure which includes a first conductive channel layer including a first conductive channel, and a first and a second doped regions respectively located at two ends of the first conductive channel, a second conductive channel layer including a second conductive channel, and a third and a fourth doped regions respectively located at two ends of the second conductive channel and a conductive buffer layer configured to reduce electrical interference between the first and the third doped regions; a first conductive layer in contact with the second doped region; a second conductive layer nested on the conductive channel structure and in contact with the first and the third doped regions; and a gate structure arranged around the first conductive channel and the second conductive channel.

Abstract: This disclosure relates to an organic electroluminescent structure and a fabrication method thereof, and a display device. The organic electroluminescent structure includes a base substrate; an anode layer formed on the base substrate, in which the anode layer comprises a plurality of anodes arranged at intervals; an organic light-emitting functional layer having a hole injection layer, in which the hole injection layer includes a plurality of hole injection blocks arranged at intervals, and each of the hole injection blocks is correspondingly formed on the second surface of one of the anodes; and a cathode layer formed at a side of the organic light-emitting functional layer facing away from the anode layer.

Abstract: An embodiment of the present application provides a manufacturing method of a semiconductor structure, including: providing a base; forming a first mask layer with a first mask pattern on the base, and etching the base with the first mask layer as a mask to form an active region; forming a plurality of discrete bitlines on the active region; sequentially stacking a first spacer layer and a second spacer layer on a side wall of the bitline; forming a sacrificial layer between the adjacent second spacer layers; forming a second mask layer with a second mask pattern on the sacrificial layer, the first mask pattern being complementary to the second mask pattern; etching the sacrificial layer with the second mask layer and the bitline as masks to form multiple contact hole structures; and etching the first spacer layer to form a gap between the second spacer layer and the bitline.

Abstract: A videoconference system acquires images during a videoconference. A still image may be analyzed to identify persons participating in the videoconference. A first frame is generated for each person and represents a subsection of an image that focuses on the face of that person. These first frames may include unpleasant components. Background segmentation is performed on each first frame to remove or diminish such unpleasant components. For example, a second frame for a person may be generated by identifying the background segments in the first frame and blurring or replacing such background segments with a virtual background. When the second frames are put together, the differences in the first frames are obscured making it more pleasing to view. A composite stream of the second frames is generated, per layout rules, and sent to the far side for improved viewing of the participants at the far side.