Abstract: A system for preventing private image data captured at an endpoint from being shared during a videoconference is provided. A user can select three-dimensional regions which will not be seen during a videoconference while areas in front of the designated regions remain viewable.

Abstract: Methods, computer program products, and/or systems are provided that perform the following operations: determining that a log multi-process debug mode is specified; obtaining a log file for debugging a source code, wherein the log file includes a plurality of log records; inserting a plurality of process identifier fields into each current log record in the log file; inserting a new log record into the log file for a created new process; and providing for performance of debugging for the source code based in part on the plurality of process identifier fields inserted into each current log record.

Abstract: A semiconductor structure includes: a base; a first conductive path including a first channel area and a first doped area and a second doped area located on two opposite ends of the first channel area; a first electrical connection structure located in the base and in contact with first doped area; a second electrical connection structure in contact with second doped area; a second conductive path including a second channel area and a third doped area and a fourth doped area located on two opposite ends of the second channel area, the third doped area being in contact with the side of the second electrical connection structure away from the base, and orthographic projection of the second conductive path on the base being at least partially non-overlapping with orthographic projection of the first conductive path on the base; and a gate structure surrounding first channel area and second channel area.

Abstract: A system for preventing private image data captured at an endpoint from being shared during a videoconference is provided. A user can select three-dimensional regions which will not be seen during a videoconference while areas in front of the designated regions remain viewable.

Abstract: The present disclosure discloses a fiber reinforce plastic (FRP) composite material pile prepared by an FRP composite material. The FRP composite material pile includes: an FRP winding pipe, an FRP pultrusion hollow profile, and a connecting device. The FRP pultrusion hollow profile includes an outer ring pipe, an inner ring pipe, and a plurality of reinforcing bars. The FRP pultrusion hollow profile is pultruded at one time by pultrusion equipment, and fiber materials thereof are arranged in the longitudinal direction of the pipe. The FRP winding pipe is provided with circumferential fiber materials by taking the FRP pultrusion hollow profile as a membrane, and forms a composite pipe section with the FRP pultrusion hollow profile. The inner ring shape of the cross section of the FRP winding pipe is matched with the FRP pultrusion hollow profile. The FRP connecting device includes connecting plates, connecting bars, and connecting pins.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and in particular to a method of manufacturing a semiconductor structure, a semiconductor structure and a memory. The method of manufacturing a semiconductor structure includes: forming a first semiconductor layer on a substrate, the first semiconductor layer including a first trench region and a to-be-doped region on two opposite sides of the first trench region; forming a word line, the word line surrounding a sidewall surface of a part of the first semiconductor layer in the first trench region, and at least a part of a projection of a part of the first semiconductor layer in the to-be-doped region on a surface of the substrate coinciding with a projection of the word line on the surface of the substrate; forming a doping body portion, the doping body portion including first dopant ions.

Abstract: A display substrate and a manufacturing method thereof, and a display device. The display substrate includes: a base substrate including a display region and a peripheral region surrounding the display region; a first light emitting element in the display region of the base substrate; and a color film structure on a display side of the first light emitting element. The color film structure includes: a first color film, including only a first pixel color film located in the display region; and a second color film, including a second pixel color film located in the display region and at least partially non-overlapping with the first pixel color film, and a first frame color film located in the peripheral region and surrounding the display region.

Abstract: An organic light-emitting diode (OLED) display substrate, a manufacturing method thereof, and a display device are disclosed. In the OLED display substrate, an anode pattern is located at a side of an insulating layer away from a base substrate and is located in an effective display region; an organic light-emitting layer is located on the anode pattern; a periphery region includes a lead wire region and a virtual region that are at least partly overlapped; a lead wire is located in the lead wire region; the virtual region is provided with a virtual anode pattern, the virtual anode pattern is insulated from the lead wire; the periphery region further includes an annular electrode surrounding the effective display region; a cathode is electrically connected with the annular electrode; the virtual region is located at an outer side of the annular electrode away from the effective display region.

Abstract: The present disclosure discloses a semiconductor memory preparation method and a semiconductor memory, relating to the technical field of semiconductors. The method includes: providing a semiconductor substrate in which transistors are formed and have an array layout; forming a film stack structure on the semiconductor substrate; forming through holes penetrating the film stack structure to expose sources of the transistors; epitaxially growing a storage node contact layer on exposed surfaces of the sources of the transistors; and forming a bottom electrode of a capacitor on a surface of the storage node contact layer.

Abstract: A system for updating/magnifying regions within one or more data frames containing a region of interest while regions outside the region of interest are not updated or are updated less frequently. Edge devices are thereby able to surgically apply super-resolution algorithms to relevant regions of image frames, thereby leveraging their overall effectiveness.

Abstract: A semiconductor structure and a forming method thereof are provided. The method for forming a semiconductor structure includes providing a base including a semiconductor substrate and a well region located on a surface of the semiconductor substrate, in which the well region includes a plurality of active pillar columns arranged at intervals along a first direction, and each of the active pillar columns includes a plurality of active pillars arranged at intervals along a second direction, in which the first direction is perpendicular to the second direction; forming a plurality of bit line trenches by etching at least the well region and a partial thickness of the semiconductor substrate at bottoms of the active pillars; and forming buried bit lines in the bit line trenches.

Abstract: The present application provides a medicament having an anti-inflammatory bowel disease function, and a preparation method therefor and an application thereof. The medicament has a structure as represented in formula I or formula II. The medicament and a pharmaceutically acceptable salt, a solvate, a prodrug, a tautomer, a stereoisomer, or a pharmaceutical composition thereof provided by the present application have a good effect on inflammatory bowel diseases, can be used for preparing medicaments for treating the inflammatory bowel diseases, and have important clinical significance and wide application prospects.

Abstract: The present disclosure relates to a clay-polyacrylate composite comprising layers of clay intercalated with polyacrylate, wherein the layers of clay comprises at least one organosilane coupling agent comprising an acrylate moiety; and wherein the polyacrylate comprises a first acrylate monomer and a second acrylate monomer having different solubility. A surfactant-free method of synthesizing the said clay-polyacrylate composite and a method for coating are also provided. In a preferred embodiment, the first acrylate monomer is a hydrophilic acrylate monomer, e.g. 2-hydroxyethyl acrylate, and the second acrylate monomer is a hydrophobic acrylate monomer, e.g. 2-ethylhexyl acrylate. The clay-acrylate composite can be used for forming a barrier coating, which exhibits low water and low oxygen permeability.

Abstract: The present disclosure discloses a semiconductor device manufacturing method and a semiconductor device, relating to the technical field of semiconductors. The method includes: providing a semiconductor substrate, the semiconductor substrate comprising a shallow trench and active areas isolated from the shallow trench; forming an oxygen-containing layer on exposed outer surfaces of the shallow trench and the active areas; filling a first sacrificial layer of a set height in the shallow trench comprising the oxygen-containing layer on its surface; forming an etch stop layer on an upper surface of the first sacrificial layer; removing the first sacrificial layer below the etch stop layer to form an air gap; filling an isolation layer on the etch stop layer in the shallow trench to form a shallow trench isolation(STI) structure containing the air gap; and etching the active areas and the (STI) structure to form wordline trenches.

Abstract: The attention level of participants is measured and then the resulting value is provided on a display of the participants. The participants are presented in a gallery view layout. The frame of each participant is colored to indicate the attention level. The entire window is tinted in colors representing the attention level. The blurriness of the participant indicates attention level. The saturation the participant indicates attention level. The window sizes vary based on attention level. Color bars are added to provide indications of percentages of attention level over differing time periods. Neural networks are used to find the faces of the participants and then develop facial keypoint values which are used to determine gaze direction, which in turn is used to develop an attention score. The attention score is then used to determine the settings of the layout.

Abstract: A heart rate detection method and an apparatus, where the method is applied to an electronic device, and the electronic device includes a heart rate sensor. The method includes detecting, by the electronic device, a current motion status of a user carrying the electronic device, determining, based on a prestored correspondence between a motion status, a startup period, and a sampling rate, a startup period and a sampling rate corresponding to the current motion status, where the startup period is a period in which the heart rate sensor is started to detect a heart rate of the user carrying the electronic device, and the sampling rate is a sampling rate of collecting heart rate data by the heart rate sensor, and starting the heart rate sensor at regular intervals based on the startup period to collect heart rate data at the sampling rate.

Abstract: The present disclosure provides a semiconductor memory device and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor memory device includes a substrate, a source structure, a laminated structure, a floating body, a trench region, a drain structure and a gate structure. The source structure is formed on the substrate. The laminated structure includes a nitride layer and an oxide layer that are alternately laminated on the source structure. The floating body is formed in the oxide layer, and a through hole is formed in the floating body along a lamination direction of the laminated structure. The trench region is formed inside the floating body, a through hole is also formed in the trench region along the lamination direction, and the trench region is in contact with the source structure.

Abstract: The present disclosure provides a semiconductor memory device and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor memory device includes a substrate, a source structure, a laminated structure, a floating body, a trench region, a drain structure and a gate structure. The source structure is formed on the substrate. The laminated structure includes a nitride layer and an oxide layer that are alternately laminated on the source structure. The floating body is formed in the oxide layer, and a through hole is formed in the floating body along a lamination direction of the laminated structure. The trench region is formed inside the floating body, a through hole is also formed in the trench region along the lamination direction, and the trench region is in contact with the source structure.

Abstract: A memory and a method for manufacturing the same are provided. The memory includes a substrate; at least one pair of transistors on a surface of the substrate, in which conductive channels of the transistors extend in a direction perpendicular to the surface of the substrate; storage layers, which each are located at one side of the transistors and are interconnected with the conductive channels of the transistors, the pair of transistors is located between two storage layers corresponding to the pair of transistors, and the storage layers are configured to store electric charges and transfer the electric charges between the storage layers and the conductive channels interconnected therewith.

Abstract: A memory and a method for manufacturing the same are provided. The memory includes a substrate; at least one pair of transistors on a surface of the substrate, in which conductive channels of the transistors extend in a direction perpendicular to the surface of the substrate; storage layers, which each are located, in the direction perpendicular to the surface of the substrate, on a side surface of each of the transistors, the storage layers are interconnected with the conductive channels of the transistors, any one of the storage layers is located between the pair of transistors, and the storage layers are configured to store electric charges and transfer the electric charges between the storage layers and the conductive channels interconnected therewith.