Patents by Inventor Kuk-Hwan Kim

Kuk-Hwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12091238
    Abstract: A photovoltaic power generation module installation support system according to the present invention comprises: a conveyor device, which assembles a plurality of photovoltaic power generation modules into one string and moves same in one direction; and a loading cart including an accommodation space in which the string moved from the conveyor device is loaded in the direction that is horizontal to the ground, wherein the conveyor device includes one or more end stoppers for providing a vertical alignment line of the photovoltaic power generation module first arranged at one end of the conveyor device.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: September 17, 2024
    Assignee: SAMSUNG C&T CORPORATION
    Inventors: Dong Shik Kim, Ji Hwan Yoon, Kuk Hwan Kim, Jae Seung Cho
  • Patent number: 12069964
    Abstract: A method for manufacturing a magnetic random access memory array incudes forming a source region within a surface of a substrate, forming an array of three-dimensional (3D) structures over the substrate, each 3D structure being separated from an adjacent 3D structure by a cavity region, depositing a channel material on a surface of at least one sidewall of each 3D structure, depositing a gate dielectric material over the channel material on the surface of the at least one sidewall of each 3D structure, forming a first isolation region in each cavity region between adjacent 3D structures over the substrate, and forming a first gate region over the first isolation region in each cavity region.
    Type: Grant
    Filed: July 9, 2022
    Date of Patent: August 20, 2024
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Publication number: 20240150113
    Abstract: A photovoltaic power generation module installation support system according to the present invention comprises: a conveyer device, which assembles a plurality of photovoltaic power generation modules into one string and moves same in one direction; and a loading cart including an accommodation space in which the string moved from the conveyer device is loaded in the direction that is horizontal to the ground, wherein the conveyer device includes one or more end stoppers for providing a vertical alignment line of the photovoltaic power generation module first arranged at one end of a conveyor.
    Type: Application
    Filed: March 11, 2022
    Publication date: May 9, 2024
    Applicant: SAMSUNG C&T CORPORATION
    Inventors: Dong Shik KIM, Ji Hwan YOON, Kuk Hwan KIM, Jae Seung CHO
  • Patent number: 11631807
    Abstract: Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: April 18, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Marcin Gajek, Michail Tzoufras, Kadriye Deniz Bozdag, Eric Ryan, Satoru Araki, Andy Walker
  • Patent number: 11586553
    Abstract: A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein further each data word of the second plurality of data words is either awaiting write verification or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and each of the plurality of secondary segments comprises at least one counter for tracking a number of valid entries stored therein.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: February 21, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Neal Berger, Susmita Karmakar, TaeJin Pyon, Kuk-Hwan Kim
  • Patent number: 11580014
    Abstract: A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments, wherein each primary segment is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries stored therein.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: February 14, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Neal Berger, Susmita Karmakar, TaeJin Pyon, Kuk-Hwan Kim
  • Publication number: 20220344580
    Abstract: A method for manufacturing a magnetic random access memory array incudes forming a source region within a surface of a substrate, forming an array of three-dimensional (3D) structures over the substrate, depositing a channel material on a surface of at least one sidewall of each 3D structure, depositing a gate electronical material over the channel material on the surface of the at least one sidewall of each 3D structure, forming a first isolation region over the substrate, and forming a first gate region over the first isolation region.
    Type: Application
    Filed: July 9, 2022
    Publication date: October 27, 2022
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 11417829
    Abstract: A three dimensional magnetic random access memory array that includes a sourceline formed on a substrate and a magnetic memory element pillar that includes a plurality of magnetic memory element pillars formed over the substrate. The three dimensional magnetic random access memory array also includes a transistor formed between the magnetic memory element pillar, the transistor being functional to electrically connect the sourceline and magnetic memory element pillar. A plurality of magnetic memory element pillars may be formed over the substrate with a transistor between each memory element pillar to selectively connect or disconnect each of the magnetic memory element pillars. The transistor can include an epitaxial semiconductor structure having a gate dielectric formed at a side of the epitaxial semiconductor and a gate material formed on the gat dielectric such that the gate dielectric material is between the gate material and the semiconductor material.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: August 16, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 11342498
    Abstract: In accordance with one embodiment, a method includes forming a cleavable donor substrate, the substrate including monocrystalline Si, forming a dielectric layer above the substrate in a film thickness direction, and cleaving the substrate into an upper portion having the dielectric layer and a lower portion. In one embodiment, the cleavable substrate is formed using a sacrificial buffer layer above the substrate in the film thickness direction, and forming a strained Si layer above the sacrificial buffer layer in the film thickness direction, followed by etching away the sacrificial buffer layer to cleave the substrate. In another embodiment, the cleavable substrate is formed by implanting ions into the substrate to a peak implant position located below an upper surface of the substrate, annealing the substrate and dielectric layer in an inert environment to form blisters at the peak implant position, and cleaving the substrate using the blisters.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 24, 2022
    Assignee: Integrated Silicon Solution (Cayman) Inc.
    Inventors: Marcin Gajek, Kuk-Hwan Kim, Dafna Beery, Amitay Levi
  • Publication number: 20220107888
    Abstract: A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments, wherein each primary segment is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries stored therein.
    Type: Application
    Filed: September 13, 2021
    Publication date: April 7, 2022
    Inventors: Neal BERGER, Susmita KARMAKAR, TaeJin PYON, Kuk-Hwan KIM
  • Publication number: 20220107900
    Abstract: A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein further each data word of the second plurality of data words is either awaiting write verification or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and each of the plurality of secondary segments comprises at least one counter for tracking a number of valid entries stored therein.
    Type: Application
    Filed: September 13, 2021
    Publication date: April 7, 2022
    Inventors: Neal BERGER, Susmita KARMAKAR, TaeJin PYON, Kuk-Hwan KIM
  • Publication number: 20220029092
    Abstract: Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.
    Type: Application
    Filed: August 16, 2021
    Publication date: January 27, 2022
    Inventors: Kuk-Hwan Kim, Dafna Beery, Marcin Gajek, Michail Tzoufras, Kadriye Deniz Bozdag, Eric Ryan, Satoru Araki, Andy Walker
  • Patent number: 11222970
    Abstract: A transistor structure, according to one embodiment, includes: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel. The second side of the vertical channel is opposite the first side of the vertical channel along a plane perpendicular to a deposition direction. A magnetic device, according to another embodiment, includes: a plurality of transistor structures, each of the transistor structures comprising: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: January 11, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 11119910
    Abstract: A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments, wherein each primary segment is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries stored therein.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: September 14, 2021
    Assignee: SPIN MEMORY, INC.
    Inventors: Neal Berger, Susmita Karmakar, TaeJin Pyon, Kuk-Hwan Kim
  • Patent number: 11119936
    Abstract: A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein further each data word of the second plurality of data words is either awaiting write verification or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and each of the plurality of secondary segments comprises at least one counter for tracking a number of valid entries stored therein.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: September 14, 2021
    Assignee: Spin Memory, Inc.
    Inventors: Neal Berger, Susmita Karmakar, TaeJin Pyon, Kuk-Hwan Kim
  • Patent number: 11107979
    Abstract: Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 31, 2021
    Assignee: Spin Memory, Inc.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Marcin Gajek, Michail Tzoufras, Kadriye Deniz Bozdag, Eric Ryan, Satoru Araki, Andy Walker
  • Patent number: D919589
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: May 18, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ye-Ran Ji, Kuk-Hwan Kim, Sang-Sik Park
  • Patent number: D926745
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: August 3, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ye-Ran Ji, Kuk-Hwan Kim, Sang-Sik Park
  • Patent number: D974317
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: January 3, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kil-Hyun Baek, Kuk-Hwan Kim, Ki-Sung Kim, Sang-Sik Park
  • Patent number: D974318
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: January 3, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kil-Hyun Baek, Kuk-Hwan Kim, Ki-Sung Kim, Sang-Sik Park