Abstract: According to one embodiment, a method includes forming, at a low temperature, a thin film transistor structure above a flexible substrate in a film thickness direction. The low temperature is less than about 200° C., and the thin film transistor structure includes a contact pad on a lower or upper surface thereof. The method also includes forming, at a high temperature, a perpendicular magnetic tunnel junction (pMTJ) structure above a rigid substrate. The high temperature is greater than about 200° C. The method also includes removing the rigid substrate from below the pMTJ structure and bonding, at the low temperature, the pMTJ structure to the thin film transistor structure using an adhesion layer. Other methods of forming flexible substrates for mounting pMTJs and systems thereof are described in accordance with more embodiments.

Abstract: A switching device, according to one embodiment, includes: a cylindrical pillar gate contact, an annular cylindrical channel which encircles a portion of the cylindrical pillar gate contact, an annular cylindrical oxide layer which encircles a portion of the annular cylindrical channel, and a source contact tab which encircles a portion of the annular cylindrical channel toward a first end of the annular cylindrical channel. Other systems are also described in additional embodiments herein which provide various different switching devices having improved components including improved annular cylindrical channel structures, improved source contacts, and/or improved cylindrical pillar gate contacts. These improved systems and components thereof may be implemented in vertical annular transistor structures in comparison to conventional surface transistor structures.

Abstract: A method of forming a cylindrical vertical transistor; the method, according to one embodiment, includes: forming a cylindrical pillar from a single block of silicon, forming an oxide layer over an exterior of the cylindrical pillar and exposed surfaces of the block of silicon, coating the oxide layer with a spin-on-glass (SOG), depositing a source mask over a majority of the SOG coating, and removing a portion of the SOG coating and underlying oxide layer, where the portion removed is defined by the source mask. Other systems and methods are also described in additional embodiments herein which provide various different improved processes of forming the cylindrical gate contacts, the source contacts, and/or the drain contacts for vertical transistor structures which also include the aforementioned cylindrical pillar channel structures and cylindrical gate in comparison to conventional surface transistor structures.

Abstract: According to one embodiment, a method includes forming an etch-stop layer above a substrate, forming a matrix layer above the etch-stop layer, forming a set of pillars above the matrix layer, the set of pillars having a predefined spacing therebetween along a plane in an element width direction and an element depth direction, the plane being normal to a film thickness direction, forming a functionalization layer above the pillars, along sides of the pillars, and above the matrix layer, forming first diblock copolymer layers above the functionalization layer, the first diblock copolymer layers self-segregating into a first polymer and a second polymer in a first pattern, removing the first polymer from the first diblock copolymer layers to create a first mask layer, and removing portions of the matrix layer to expose portions of the etch-stop layer positioned therebelow and create a second pattern in the matrix layer.

Abstract: The various implementations described herein include methods, devices, and systems for performing operations on memory devices. In one aspect, a memory device includes: (1) a magnetic memory component; and (2) a current selector component coupled to the magnetic memory component, the current selector component including: (a) a first transistor having a first gate with a corresponding first threshold voltage; and (b) a second transistor having a second gate with a corresponding second threshold voltage, distinct from the first threshold voltage; where the second transistor is coupled in parallel with the first transistor.

Abstract: A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words into an error buffer associated with the memory bank wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. Additionally, the method comprises monitoring an occupancy level of the error buffer and determining if the occupancy level of the error buffer has increased beyond a predetermined threshold. Subsequently, responsive to a determination that the occupancy level of the error buffer has increased beyond the predetermined threshold, increasing a write voltage of the memory bank, wherein subsequent write operations are performed at a higher write voltage.

Abstract: An electronic device includes a camera module capturing an image, a sensor module recognizing a signal associated with the electronic device or an external object, a first display and a second display, each of which is configured to output content, a memory, and a processor electrically connected to the camera module, the first display, the second display, and the memory. The processor is configured to determine whether the electronic device enters a first state, to capture a source image by using the camera module, when entering the first state, and to generate a first output image output on the first display or a second output image output on the second display based on the source image.

Abstract: According to one embodiment, a method includes forming a bottom electrode layer above a substrate in a film thickness direction, forming a source layer above the bottom electrode layer in the film thickness direction, forming an impact ionization channel (i-channel) layer above the source layer in the film thickness direction, forming a drain layer above the i-channel layer in the film thickness direction, forming an upper electrode layer above the drain layer in the film thickness direction to form a stack that includes the bottom electrode layer, the source layer, the i-channel layer, the drain layer, and the upper electrode layer, and forming a gate layer positioned on sides of the i-channel layer along a plane perpendicular to the film thickness direction in an element width direction. The gate layer is formed in a position closer to the drain layer than the source layer.

Abstract: A processor-implemented method, according to one embodiment, includes: activating a subset of a plurality of p-MTJ cells oriented in one or more columns of a MRAM array. Activating the subset of p-MTJ cells includes: applying a first voltage to a gate terminal of the transistor in each of the p-MTJ cells in parallel, applying a second voltage to a first end of the MTJ sensor in each of the p-MTJ cells in parallel, and applying a third voltage to a drain terminal of the transistor in each of the p-MTJ cells in parallel. The processor-implemented method also includes: monitoring the activated subset of p-MTJ cells, determining whether any of the activated p-MTJ cells have failed, and in response to determining that an activated p-MTJ cell has failed, physically locating the failed p-MTJ cell. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.

Abstract: A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.

Abstract: A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.

Abstract: A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.

Abstract: In one embodiment, an apparatus includes lower electrodes positioned below a surface of a substrate, the substrate including crystalline Si, a plurality of strap regions positioned above the lower electrodes and below sets of pillars of Si, the pillars rising above the substrate, the sets of pillars being aligned in a first direction along a plane perpendicular to a film thickness direction, and the strap regions extending above a surface of the substrate, silicide junctions positioned between each of the strap regions and a corresponding lower electrode positioned therebelow, upper electrodes positioned above each of the pillars, gate dielectric layers positioned on sides of the pillars to a height greater than a lower edge of the upper electrodes, and gate layers positioned on sides of the gate dielectric layers in a second direction along the plane and perpendicular to the first direction that transverse a plurality of sets of pillars.

Abstract: An electronic device is provided. The electronic device includes a housing including a first surface facing a first direction, a second surface facing a second direction opposite to the first direction, and a side surface extending between and along a perimeter of the first surface and the second surface, a cover glass corresponding to at least the first surface, a display panel disposed under the cover glass and including an active area exposed through the cover glass, an inactive area surrounding the active area, and a printed circuit board connection portion connected to one end of the inactive area, wherein at least one opening or at least one cutaway portion is formed in the display panel, and a camera module disposed in a space formed by the at least one opening or the at least one cutaway portion and exposed through the cover glass.

Abstract: An electronic device is provided. The electronic device includes a housing including a first surface facing a first direction, a second surface facing a second direction opposite to the first direction, and a side surface extending between and along a perimeter of the first surface and the second surface, a cover glass corresponding to at least the first surface, a display panel disposed under the cover glass and including an active area exposed through the cover glass, an inactive area surrounding the active area, and a printed circuit board connection portion connected to one end of the inactive area, wherein at least one opening or at least one cutaway portion is formed in the display panel, and a camera module disposed in a space formed by the at least one opening or the at least one cutaway portion and exposed through the cover glass.

Abstract: An attaching and detaching device of a protection cover for protecting an electronic device is provided. The attaching and detaching device includes one or more hook units provided on the protection cover; and one or more attaching and detaching units which are provided at positions corresponding to the hook units on a rear surface of the electronic device, and are latched and fixed to or released from the hook units.

Abstract: Operating characteristics associated with non-volatile two-terminal memory can be modified post-fabrication, e.g., by a controller that controls the non-volatile two-terminal memory. As a result, two-terminal memory arrays included in memory devices (e.g., memory cards, solid-state drives, etc.) can be flexibly modified to provide numerous advantages over other types of non-volatile memory.

Abstract: A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer.