Abstract: A magnetic memory element having voltage controlled magnetic anisotropy for active control of switching energy (delta). The magnetic memory element can be formed as a pillar structure having a magnetic free layer a magnetic reference layer and a non-magnetic barrier layer located between the magnetic free layer and the magnetic reference layer. A dielectric wall is formed around the side of the magnetic free layer and an electrically conductive program line is formed around the dielectric wall, such that the dielectric wall separates the program line from the magnetic free layer. The electrically conductive program line is electrically connected with circuitry to selectively apply a gate voltage to the electrically conductive program line and across the dielectric layer. The circuitry can include a voltage source switching circuitry such as a transistor. The gate voltage advantageously reduces perpendicular magnetic anisotropy in the magnetic free layer, thereby reducing switching energy.

Abstract: A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words into an error buffer associated with the memory bank wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. Additionally, the method comprises monitoring an occupancy level of the error buffer and determining if the occupancy level of the error buffer has increased beyond a predetermined threshold. Subsequently, responsive to a determination that the occupancy level of the error buffer has increased beyond the predetermined threshold, increasing a write voltage of the memory bank, wherein subsequent write operations are performed at a higher write voltage.

Abstract: A method for forming three-dimensional magnetic memory arrays by forming crystalized silicon structures from amorphous structures in the magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSi2 or CoSi2 and also causes the underlying amorphous silicon to crystallize.

Abstract: A method for crystalized silicon structures from amorphous structures in a magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSi2 or CoSi2 and also causes the underlying amorphous silicon to crystallize.

Abstract: The various implementations described herein include methods, devices, and systems for performing operations on memory devices. In one aspect, a memory device includes: (1) a first charge storage device having a first gate with a corresponding first threshold voltage, the first charge storage device configured to store charge corresponding to one or more first bits; and (2) a second charge storage device having a second gate with a corresponding second threshold voltage, distinct from the first threshold voltage, the second charge storage device configured to store charge corresponding to one or more second bits; where the second charge storage device is coupled in parallel with the first charge storage device.

Abstract: A three dimensional magnetic random access memory array that includes a sourceline formed on a substrate and a magnetic memory element pillar that includes a plurality of magnetic memory element pillars formed over the substrate. The three dimensional magnetic random access memory array also includes a transistor formed between the magnetic memory element pillar, the transistor being functional to electrically connect the sourceline and magnetic memory element pillar. A plurality of magnetic memory element pillars may be formed over the substrate with a transistor between each memory element pillar to selectively connect or disconnect each of the magnetic memory element pillars. The transistor can include an epitaxial semiconductor structure having a gate dielectric formed at a side of the epitaxial semiconductor and a gate material formed on the gat dielectric such that the gate dielectric material is between the gate material and the semiconductor material.

Abstract: A method of forming a transistor, according to one embodiment, includes: forming an doped material, depositing an oxide layer on the doped material, depositing a conducting layer on the oxide layer, patterning the conducting layer to form at least two word lines, depositing a nitride layer above the at least two word lines, defining at least two hole regions, at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes, depositing a gate dielectric layer on the nitride layer and in the at least two holes, depositing a protective layer on the gate dielectric layer, etching in each of the at least two holes down to the doped material, and removing a remainder of the protective layer.

Abstract: A magnetic device, according to one approach, includes: a plurality of perpendicular magnetic tunnel junction (p-MTJ) cells, each p-MTJ cell having a transistor and a magnetic tunnel junction (MTJ) sensor. Moreover, each of the transistors includes a drain terminal, a source terminal, and a gate terminal. The magnetic device also includes: a first common word line coupled to the gate terminal of each transistor in a first subset of the plurality of p-MTJ cells, a first common bit line coupled to a first end of each MTJ sensor in a second subset of the plurality of p-MTJ cells, and a first common source line coupled to the drain terminal of each transistor in the first subset. A second end of each of the MTJ sensors in the second subset is coupled to the source terminal of each respective transistor in the second subset.

Abstract: An annular device is provided. The annular device includes a first transistor including a first input terminal and a second transistor including a second input terminal. The first input terminal and the second input terminal extend radially outward from the annular device, and wherein the first input terminal is aligned with the second input terminal.

Abstract: A Magnetic Tunnel Junction (MTJ) device can include an array of cells. The array of cells can include a plurality of source lines disposed in columns, set of selectors coupled to respective source lines, MJT structures coupled to respective selectors and a plurality of bit lines disposed in rows and coupled to respective sets of MTJ structures. The array of cells can also include buffers coupled between respective selectors and respective MTJ structures. In addition, multiple arrays can be stacked on top of each other to implement vertical three-dimensional (3D) MTJ devices.

Abstract: Methods of fabricating devices including arrays of integrated Magnetic Tunnel Junctions (MTJs) and corresponding selectors in an array of cells. The array of cells can include a plurality of source lines disposed in columns, set of selectors coupled to respective source lines, MJT structures coupled to respective selectors and a plurality of bit lines disposed in rows and coupled to respective sets of MTJ structures. The array of cells can also include buffers coupled between respective selectors and respective MTJ structures. In addition, multiple arrays can be fabricated on top of each other to implement vertical three-dimensional (3D) MTJ devices.

Abstract: A switching device, according to one embodiment, includes: a cylindrical pillar gate contact, an annular cylindrical channel which encircles a portion of the cylindrical pillar gate contact, an annular cylindrical oxide layer which encircles a portion of the annular cylindrical channel, and a source contact tab which encircles a portion of the annular cylindrical channel toward a first end of the annular cylindrical channel. Other systems are also described in additional embodiments herein which provide various different switching devices having improved components including improved annular cylindrical channel structures, improved source contacts, and/or improved cylindrical pillar gate contacts. These improved systems and components thereof may be implemented in vertical annular transistor structures in comparison to conventional surface transistor structures.

Abstract: According to one embodiment, a method includes forming a drain contact above a channel, each having a hollow circular cross-section thereof along a plane perpendicular to a film thickness direction, forming gate dielectric layers on sides of the drain contact and the channel, forming a source line positioned below the channel that is electrically coupled to a plurality of channels in a direction along the plane, forming gate layers on sides of the gate dielectric layers, where an inner gate layer fills a hole through a center of a center concentric circular cross-section of the gate dielectric layers along the plane, and where an outer gate layer surrounds an outside concentric circular cross-section of the gate dielectric layers along the plane, forming an electrode above the upper surface of the drain contact, and forming a fourth insulative layer on sides of the electrode along the plane.

Abstract: The various implementations described herein include methods, devices, and systems for performing operations on memory devices. In one aspect, a memory device a magnetic memory component and a current selector component coupled to the magnetic memory component. The current selector component includes a first transistor having a first gate with a corresponding first threshold voltage. The first transistor comprises a charge storage layer configured to selectively store charge so as to adjust a current through the first transistor. The memory device further includes control circuitry configured to determine a bit error rate of the magnetic memory component and adjust a charge stored in the charge storage layer based on the determined bit error rate.

Abstract: Disclosed is a portable electronic device including a housing including a first surface and a second surface facing a direction opposite to the first surface, a display including a touchscreen panel exposed through the first surface of the housing and having a substantially rectangular shape, wherein the display has a first side and a third side extending with a first length in a first direction, and a second side and a fourth side substantially perpendicular to the first direction and extending with a second length which is less than the first length, and wherein a ratio of the first length to the second length is x:9, in which the x is equal to or greater than 16, a wireless communication circuit, a processor, and a memory.

Abstract: According to one embodiment, an apparatus includes: a substrate, an array of 3D structures, where each 3D structure includes a source region having a first conductivity, a series of layers positioned in a vertical direction, a channel material on a surface of at least one sidewall of each 3D structure, and a gate dielectric material on the channel material. The series of layers includes a dielectric layer positioned above the substrate, a plurality of a set of MTJ layers positioned above the dielectric layer, and a buffer layer positioned in between the dielectric layer and each set of MTJ layers thereof. The magnetic memory device further includes an isolation region positioned between the 3D structures and at least one gate region positioned above the isolation region, where each gate region is coupled to at least one sidewall of each 3D structure.

Abstract: A method, according to one embodiment, includes: forming an annular cylindrical channel from a single block of electrically conductive material; forming an oxide layer over exposed surfaces of the annular cylindrical channel and exposed surfaces of the block of electrically conductive material; removing a portion of the oxide layer from an exterior base of the annular cylindrical channel, thereby forming a source contact recess which surrounds the base of the annular cylindrical channel; ion-implanting the exposed electrically conductive material substrate at a base of the source contact recess; and depositing a silicide material in the source contact recess, thereby forming a source contact tab.

Abstract: According to one embodiment, an apparatus includes a bottom electrode layer positioned above a substrate in a film thickness direction, a source layer positioned above the bottom electrode layer in the film thickness direction, an impact ionization channel (i-channel) layer positioned above the source layer in the film thickness direction, a drain layer positioned above the i-channel layer in the film thickness direction, an upper electrode layer positioned above the drain layer in the film thickness direction that forms a stack that includes the bottom electrode layer, the source layer, the i-channel layer, the drain layer, and the upper electrode layer, and a gate layer positioned on sides of the i-channel layer along a plane perpendicular to the film thickness direction in an element width direction. The gate layer is positioned closer to the drain layer than the source layer. Other apparatuses are described in accordance with more embodiments.