Patents by Inventor Kuk-Hwan Kim

Kuk-Hwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Two-terminal memory compatibility with NAND flash memory set features type mechanisms
    Patent number: 9727258
    Abstract: Operating characteristics associated with NAND flash memory can be modified and/or emulated to support corresponding operating characteristics for two-terminal memory. As a result, NAND flash memory modules included in conventional NAND flash memory devices (e.g., memory cards, solid-state drives, etc.) can be replaced with two-terminal memory without substantial changes to manufacturing infrastructure associated with the manufacture of these NAND flash memory devices.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: August 8, 2017
    Assignee: CROSSBAR, INC.
    Inventors: Hagop Nazarian, Kuk-Hwan Kim
  • Resistive memory device and fabrication methods
    Patent number: 9673255
    Abstract: A method for forming a resistive memory device includes providing a substrate comprising a first metal material, forming a conductive silicon-bearing layer on top of the first metal material, wherein the conductive silicon-bearing layer comprises an upper region and a lower region, and wherein the lower region is adjacent to the first metal material, forming an amorphous layer from the upper region of the conductive silicon-bearing layer, and disposing an active metal material above the amorphous layer.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: June 6, 2017
    Assignee: CROSSBAR, INC.
    Inventors: Sung Hyun Jo, Kuk-Hwan Kim, Tanmay Kumar
  • Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects
    Patent number: 9570683
    Abstract: Providing for three-dimensional memory cells having enhanced electric field characteristics and/or memory cells located at broken interconnects is described herein. By way of example, a two-terminal memory cell can be constructed from a layered stack of materials, where respective layers are arranged along a direction that forms a non-zero angle to a normal direction of a substrate surface upon which the layered stack of materials is constructed. In some aspects, the direction can be orthogonal to or substantially orthogonal to the normal direction. In other aspects, the direction can be less than orthogonal to the normal direction. Where an internal angle of the memory cell forms a non-orthogonal angle, an enhanced electric field or current density can result, providing improved switching times and memory performance.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: February 14, 2017
    Assignee: CROSSBAR, INC.
    Inventors: Sung Hyun Jo, Kuk-Hwan Kim, Joanna Bettinger
  • Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects
    Patent number: 9564587
    Abstract: Providing for three-dimensional memory cells having enhanced electric field characteristics and/or memory cells located at broken interconnects is described herein. By way of example, a two-terminal memory cell can be constructed from a layered stack of materials, where respective layers are arranged along a direction that forms a non-zero angle to a normal direction of a substrate surface upon which the layered stack of materials is constructed. In some aspects, the direction can be orthogonal to or substantially orthogonal to the normal direction. In other aspects, the direction can be less than orthogonal to the normal direction. Where an internal angle of the memory cell forms a non-orthogonal angle, an enhanced electric field or current density can result, providing improved switching times and memory performance.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: February 7, 2017
    Assignee: CROSSBAR, INC.
    Inventors: Sung Hyun Jo, Kuk-Hwan Kim, Joanna Bettinger
  • Silicon based nanoscale crossbar memory
    Patent number: 9520557
    Abstract: The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: December 13, 2016
    Assignee: The Regents of the University of Michigan
    Inventors: Wei Lu, Sung Hyun Jo, Kuk-Hwan Kim
  • Controlling on-state current for two-terminal memory
    Patent number: 9520561
    Abstract: Provision of fabrication, construction, and/or assembly of a memory device including a two-terminal memory portion is described herein. The two-terminal memory device fabrication can provide enhanced capabilities in connection with precisely tuning on-state current over a greater possible range.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: December 13, 2016
    Assignee: CROSSBAR, INC.
    Inventors: Kuk-Hwan Kim, Ping Lu, Chen-Chun Chen, Sung Hyun Jo
  • Thin film transistor of display apparatus
    Patent number: 9450106
    Abstract: Disclosed is a thin film transistor (TFT) of a display apparatus which reduces a leakage current caused by a hump and decreases screen defects. The TFT includes an active layer and a first gate electrode with a gate insulator therebetween, and a source electrode and a drain electrode respectively disposed at both ends of the active layer. The gate electrode branches as a plurality of lines and overlaps the active layer. The active layer includes one or more channel areas between the source electrode and the drain electrode, one or more dummy areas, and a plurality of link areas between the one or more channel areas to connect the one or more channel areas in one pattern. A length of each of the one or more dummy areas extends from an edge of a corresponding channel area.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: September 20, 2016
    Assignee: LG Display Co., Ltd.
    Inventors: Sang Kug Han, Ki Sul Cho, Choon Ho Park, Jin Ho Choi, Kuk Hwan Kim, Soo Hong Kim, Eun Ji Ham, Byoung Cheol Song
  • NOBLE METAL / NON-NOBLE METAL ELECTRODE FOR RRAM APPLICATIONS
    Publication number: 20160233422
    Abstract: A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer.
    Type: Application
    Filed: April 20, 2016
    Publication date: August 11, 2016
    Inventors: Sung Hyun Jo, Kuk-Hwan Kim, Tanmay Kumar
  • Resistive random access memory with non-linear current-voltage relationship
    Patent number: 9406379
    Abstract: Providing for fabrication, construction, and/or assembly of a resistive random access memory (RRAM) cell is described herein. The RRAM cell can exhibit a non-linear current-voltage relationship. When arranged in a memory array architecture, these cells can significantly mitigate sneak path issues associated with conventional RRAM arrays.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: August 2, 2016
    Assignee: CROSSBAR, INC.
    Inventors: Sung Hyun Jo, Kuk-Hwan Kim
  • Low temperature deposition for silicon-based conductive film
    Patent number: 9269898
    Abstract: Providing for low temperature deposition of silicon-based electrical conductor for solid state memory is described herein. In various disclosed embodiments, the silicon-based conductor can form an electrode of a memory cell, an interconnect between conductive components of an electronic device, a conductive via, a wire, and so forth. Moreover, the silicon-based electrical conductor can be formed as part of a monolithic process incorporating complementary metal oxide semiconductor (CMOS) device fabrication. In particular embodiments, the silicon-based electrical conductor can be a p-type silicon germanium compound, that is activated upon deposition at temperatures compatible with CMOS device fabrication.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: February 23, 2016
    Assignee: Crossbar, Inc.
    Inventors: Steven Patrick Maxwell, Kuk-Hwan Kim, Sung Hyun Jo
  • SILICON BASED NANOSCALE CROSSBAR MEMORY
    Publication number: 20160005964
    Abstract: The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials.
    Type: Application
    Filed: September 17, 2015
    Publication date: January 7, 2016
    Inventors: Wei LU, Sung Hyun JO, Kuk-Hwan KIM
  • THIN FILM TRANSISTOR OF DISPLAY APPARATUS
    Publication number: 20150380567
    Abstract: Disclosed is a thin film transistor (TFT) of a display apparatus which reduces a leakage current caused by a hump and decreases screen defects. The TFT includes an active layer and a first gate electrode with a gate insulator therebetween, and a source electrode and a drain electrode respectively disposed at both ends of the active layer. The gate electrode branches as a plurality of lines and overlaps the active layer. The active layer includes one or more channel areas between the source electrode and the drain electrode, one or more dummy areas, and a plurality of link areas between the one or more channel areas to connect the one or more channel areas in one pattern. A length of each of the one or more dummy areas extends from an edge of a corresponding channel area.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 31, 2015
    Inventors: Sang Kug HAN, Ki Sul CHO, Choon Ho PARK, Jin Ho CHOI, Kuk Hwan KIM, Soo Hong KIM, Eun Ji HAM, Byoung Cheol SONG
  • Silicon based nanoscale crossbar memory
    Patent number: 9159416
    Abstract: The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: October 13, 2015
    Assignee: The Regents of The University of Michigan
    Inventors: Wei Lu, Sung Hyun Jo, Kuk-Hwan Kim
  • LOW TEMPERATURE DEPOSITION FOR SILICON-BASED CONDUCTIVE FILM
    Publication number: 20150228894
    Abstract: Providing for low temperature deposition of silicon-based electrical conductor for solid state memory is described herein. In various disclosed embodiments, the silicon-based conductor can form an electrode of a memory cell, an interconnect between conductive components of an electronic device, a conductive via, a wire, and so forth. Moreover, the silicon-based electrical conductor can be formed as part of a monolithic process incorporating complementary metal oxide semiconductor (CMOS) device fabrication. In particular embodiments, the silicon-based electrical conductor can be a p-type silicon germanium compound, that is activated upon deposition at temperatures compatible with CMOS device fabrication.
    Type: Application
    Filed: July 25, 2014
    Publication date: August 13, 2015
    Inventors: Steven Patrick MAXWELL, Kuk-Hwan KIM, Sung Hyun JO
  • Controlling on-state current for two-terminal memory
    Patent number: 9093635
    Abstract: Provision of fabrication, construction, and/or assembly of a memory device including a two-terminal memory portion is described herein. The two-terminal memory device fabrication can provide enhanced capabilities in connection with precisely tuning on-state current over a greater possible range.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: July 28, 2015
    Assignee: Crossbar, Inc.
    Inventors: Kuk-Hwan Kim, Ping Lu, Chen-Chun Chen, Sung Hyun Jo
  • PROTECTION COVER
    Publication number: 20150189962
    Abstract: An attaching and detaching device of a protection cover for protecting an electronic device is provided. The attaching and detaching device includes one or more hook units provided on the protection cover; and one or more attaching and detaching units which are provided at positions corresponding to the hook units on a rear surface of the electronic device, and are latched and fixed to or released from the hook units.
    Type: Application
    Filed: November 21, 2014
    Publication date: July 9, 2015
    Inventors: Jung-Min YEO, Kuk-Hwan KIM, In-Young YEO, Jae-Ho BAlK, Min-Hyouk LEE
  • RESISTIVE MEMORY DEVICE AND FABRICATION METHODS
    Publication number: 20150144863
    Abstract: A method for forming a resistive memory device includes providing a substrate comprising a first metal material, forming a conductive silicon-bearing layer on top of the first metal material, wherein the conductive silicon-bearing layer comprises an upper region and a lower region, and wherein the lower region is adjacent to the first metal material, forming an amorphous layer from the upper region of the conductive silicon-bearing layer, and disposing an active metal material above the amorphous layer.
    Type: Application
    Filed: January 14, 2015
    Publication date: May 28, 2015
    Inventors: Sung Hyun JO, Kuk-Hwan KIM, Tanmay KUMAR
  • Case for electronic device
    Patent number: D734340
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: July 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kuk-Hwan Kim, Jae-Ho Baik, Jung-Min Yeo, Min-Hyouk Lee
  • Electronic device
    Patent number: D763252
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: August 9, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Hyouk Lee, Jae-Ho Baik, Kuk-Hwan Kim, Sung-Hoon Hong
  • Electronic device
    Patent number: D771620
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: November 15, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kuk-Hwan Kim, Jae-Ho Baik, Min-Hyouk Lee