Abstract: Technologies for fiber array unit (FAU) lid designs are disclosed. In one embodiment, channels in the lid allow for suction to be applied to fibers that the lid covers, pulling the fibers into place in a V-groove. The suction can hold the fibers in place as the fiber array unit is mated with a photonic integrated circuit (PIC) die. Additionally or alternatively, channels can be on pitch, allowing for pulling the FAU towards a PIC die as well as sensing the position and alignment of the FAU to the PIC die. In another embodiment, a warpage amount of a PIC die is characterized, and a FAU lid with a similar warpage is fabricated, allowing for the FAU to position fibers correctly relative to waveguides in the PIC die. In another embodiment, a FAU has an extended lid, which can provide fiber protection as well as position and parallelism tolerance control.

Abstract: Systems and methods for managing asynchronous resets in an SoC have been described. In an illustrative, non-limiting embodiment, a reset generation circuit in an SoC, may include a first reset generation circuit configured to enable a first reset signal based, at least in part, upon a clock signal and an indication to reset. The reset generation circuit may also include a second reset generation circuit coupled to the first reset generation circuit, in which the second reset generation circuit is configured to enable a second reset signal after the first reset signal is enabled. The first reset signal and the second reset signal are both provided to a component of the SoC.

Abstract: A low voltage differential signaling (LVDS) receiver includes a receiver circuit including first and second inputs coupled to first and second conductive pads, respectively, and an output coupled to an input of a digital controller, and a dummy transmitter circuit including a first input coupled to receive a common mode voltage (VCM) tune signal, a second input coupled to a loopback input signal, a third input coupled to a loopback enable signal, a first output coupled to the first input of the receiver circuit, and a second output coupled to the second input of the receiver circuit. When a test mode of operation is enabled, the digital controller asserts the loopback enable signal, and the dummy transmitter circuit generates a pair of test differential signals based on the VCM tune signal, wherein the VCM tune signal varies to test the LVDS receiver over a range of common mode voltages.

Abstract: An approach is provided for augmenting text of a small class for text classification. An imbalanced dataset is received. A small class is identified. The small class includes initial text records in the imbalanced dataset. A balanced dataset is generated from the imbalanced dataset by augmenting the initial text records by using weighted word scores indicating respective measures of importance of words in classes in the imbalanced dataset. The balanced dataset is sent to a supervised machine learning model. The supervised machine learning model is trained on the balanced dataset. Using the supervised machine learning model which employs the augmented initial text records, a text classification of a new dataset is performed. The domain of the new dataset matches the domain of the imbalanced dataset.

Abstract: A first circuit path communicates a first, asynchronous, signal, and a second path communicates a second signal. A schmoo delay circuit receives the first and second signals and includes shmoo control circuitry and a delay generator. The delay generator receives a delay selector signal from the shmoo control circuitry indicative of an amount of delay. The shmoo delay circuit provides a delayed version of at least one of the first or second signals. A first logic circuit receives the delayed version of the at least one of the first signal or the second signal, and a second logic circuit receives another one of the first signal or the second signal. The shmoo control circuitry modifies the delay selector signal to sweep through a set of different delay amounts applied by the delay generator to generate delayed versions of the at least one of the first signal or the second signal.

Abstract: A first power supply pad is configured to provide a first power supply to a power domain of the SoC in which the first power supply pad is configured to receive the first power supply from a source external to the SoC. A first signal pad is configured to receive a power ready signal from external the SoC which indicates when the first power supply to the power domain is fully powered up. A first power detector is configured to provide a first power detected output, which, when asserted, indicates presence of a power supply voltage on the first power supply pad. A fault detection circuit coupled to the first power detector and the first signal pad is configured to generate a set of fault flags in response to monitoring a relationship between the first power detected output and a logic state of the power ready signal.

Abstract: A system-on-chip (SoC) having a switchable power domain capable of being placed in a standby mode during which a power supply of the switchable power domain is gated and having an always-on power domain. The always-on power domain includes an input sampling circuit, and the switchable power domain includes an input/output (IO) circuit configured to, during normal operation, receive data at a corresponding signal pin when an input buffer of the IO circuit is enabled, in which the corresponding signal pin is coupled to the input sampling circuit. The input sampling circuit is configured to, while the switchable power domain is entering the standby mode but before the power supply is gated, provide an override input enable signal to enable the input buffer of the IO circuit, sample an input bit value on the corresponding signal pin, and store the sampled bit value to provide an injection current fault indicator.

Abstract: The present disclosure is directed to an artificial intelligence (AI) assisted monitoring system that uses cameras to recognize a product being moved by the user across the self-checkout unit and verifying whether the product was scanned at the point-of-sale terminal based on timestamp information associated with when the product was moved across the self-checkout unit to identify miss scan thefts.

Abstract: A method and system for generating and utilizing a personalized compression system includes receiving a first writing, extracting features from the first writing into hash values, generating a plurality of summaries for the first writing, each summary of the plurality of summaries having a different length, causing display of at least one summary of the plurality of summaries on a client, receiving, from a user of the client, an indication of a selection based on the displayed at least one of summary of the plurality of summaries, and refining the baseline machine learning model based on the hash values and the selected summary to generate a personalized machine learning model.

Abstract: Systems and methods for managing asynchronous resets in an SoC have been described. In an illustrative, non-limiting embodiment, a reset generation circuit in an SoC, may include a first reset generation circuit configured to enable a first reset signal based, at least in part, upon a clock signal and an indication to reset. The reset generation circuit may also include a second reset generation circuit coupled to the first reset generation circuit, in which the second reset generation circuit is configured to enable a second reset signal after the first reset signal is enabled. The first reset signal and the second reset signal are both provided to a component of the SoC.

Abstract: A packaged die including a first and a second power supply pad configured to provide a first and a second power supply voltage, respectively, and circuitry powered by the first power supply voltage. A power pad handling circuitry includes a selectively enablable pull-down path coupled between the first power supply pad and the second power supply pad, a storage circuit configured to store a pull-down path enable bit, a clock input coupled to receive a boot clock, and an asynchronous input coupled to receive a power-on-reset (POR) signal. In response to assertion of the POR signal, the pull-down pat is enabled regardless of any signal received at the clock input and regardless the value of the pull-down path enable bit. When reset has completed, a value of the pull-down path enable bit is provided upon an active edge of the boot clock to selectively enable the pull-down path.

Abstract: A system-on-chip (SoC) having a switchable power domain capable of being placed in a standby mode during which a power supply of the switchable power domain is gated and having an always-on power domain. The always-on power domain includes an input sampling circuit, and the switchable power domain includes an input/output (IO) circuit configured to, during normal operation, receive data at a corresponding signal pin when an input buffer of the IO circuit is enabled, in which the corresponding signal pin is coupled to the input sampling circuit. The input sampling circuit is configured to, while the switchable power domain is entering the standby mode but before the power supply is gated, provide an override input enable signal to enable the input buffer of the IO circuit, sample an input bit value on the corresponding signal pin, and store the sampled bit value to provide an injection current fault indicator.

Abstract: Analog-to-digital converters (ADCs) of an integrated circuit includes a first set of ADCs and second set of ADCs in which the ADCs of the first set are of a different type than the ADCs of the second set. On-chip testing of the ADCs includes calibrating an N-bit differential digital-to-analog converter (DAC) and storing a pair of calibration codes for each of 2N possible DAC input codes for the DAC in an on-chip memory. The first set of ADCs is tested using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC. Subsequently, the second set of ADCs is tested using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, in which M is less than N. During the testing of the second set of ADCs, a portion of the calibration codes stored in the on-chip memory is overwritten.

Abstract: A packaged die including a first and a second power supply pad configured to provide a first and a second power supply voltage, respectively, and circuitry powered by the first power supply voltage. A power pad handling circuitry includes a selectively enablable pull-down path coupled between the first power supply pad and the second power supply pad, a storage circuit configured to store a pull-down path enable bit, a clock input coupled to receive a boot clock, and an asynchronous input coupled to receive a power-on-reset (POR) signal. In response to assertion of the POR signal, the pull-down pat is enabled regardless of any signal received at the clock input and regardless the value of the pull-down path enable bit. When reset has completed, a value of the pull-down path enable bit is provided upon an active edge of the boot clock to selectively enable the pull-down path.

Abstract: A tamper evident package for secure delivery of a product is disclosed. The tamper evident packaging includes a plurality of sidewalls having a closure providing access to an interior compartment of the packaging. The closure includes a closure slide that urges a closure seal into cooperative engagement during movement of the closure slide. Cooperating ratchet teeth are provided in the closure slide and at a closed end of the closure to retain the closure slide in a locked position. The closure slide includes a land for carrying a unique identifier code. The unique identifier code is visible through a window in the closure when the closure slide is in the locked position. The tamper evident packaging may be used with a product delivery service where the unique identifier code is used to identify an order through a packing of the product through receipt of the product by the customer.

Abstract: Analog-to-digital converters (ADCs) of an integrated circuit includes a first set of ADCs and second set of ADCs in which the ADCs of the first set are of a different type than the ADCs of the second set. On-chip testing of the ADCs includes calibrating an N-bit differential digital-to-analog converter (DAC) and storing a pair of calibration codes for each of 2N possible DAC input codes for the DAC in an on-chip memory. The first set of ADCs is tested using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC. Subsequently, the second set of ADCs is tested using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, in which M is less than N. During the testing of the second set of ADCs, a portion of the calibration codes stored in the on-chip memory is overwritten.

Abstract: The present invention discloses a dual mode fuel tank leakage detector (100), comprising of an electromechanical valve (1) with a canister port, an engine control unit, pump assembly, a sensor (3) and works in pressure condition by comparing a measured pressure with reference pressure; in case there is leakage then the pressure is not upto the reference pressure within time interval. In case of no leakage, the pressure will be equal/above than the reference pressure, the leakage detector (100) works in vacuum condition by comparing a measured leakage with a reference leakage, in case there is a leakage the measured vacuum is not able to reach to the reference vacuum within a time interval and when there is no leakage, the measured vacuum will be equal or above from the reference vacuum and fuel tank leakage detector (100) enables to monitor leakage detection either in vacuum or pressure conditions.

Abstract: In non-limiting examples of the present disclosure, systems, methods and devices for determining image compression optimums are provided. An image may be processed with a machine learning model that has been trained to identify object types in digital images. A first object and a first object type of the first object may be identified in the image. A first compressed version of the image may be generated, wherein the first compressed version has a first storage size. The first object and the first object type of the first object may be identified in the first compressed version of the image. A second compressed version of the image may be generated based on the identification of the first object and the first object type in the first compressed version of the image. The second compressed version may have a smaller storage size than the first storage size.

Abstract: The present invention relates to an oil control solenoid valve with improved pressure balance for high pressure applications and a method of assembling thereof. More particularly, the present invention provides an oil control solenoid valve (101) with a pressure balance assembly comprising of a fixed sleeve (2) with at least one inlet and one outlet, a movable plunger (1) having two ends and at least one bush (3) and the method of assembling thereof thus providing the pressure balance at both the ends of the plunger (1).

Abstract: The present invention relates to a system for monitoring plunger movement in non-energized condition in real time. More particularly, the present invention relates to a system comprising a plunger, a locking pin, a permanent magnet and a multi-point sensor to measure the position of plunger in a non-energized condition and to improve the automatic shut off or start on the pump.