Patents by Inventor Kumar Abhishek

Kumar Abhishek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240353479
    Abstract: A first power supply pad is configured to provide a first power supply to a power domain of the SoC in which the first power supply pad is configured to receive the first power supply from a source external to the SoC. A first signal pad is configured to receive a power ready signal from external the SoC which indicates when the first power supply to the power domain is fully powered up. A first power detector is configured to provide a first power detected output, which, when asserted, indicates presence of a power supply voltage on the first power supply pad. A fault detection circuit coupled to the first power detector and the first signal pad is configured to generate a set of fault flags in response to monitoring a relationship between the first power detected output and a logic state of the power ready signal.
    Type: Application
    Filed: August 30, 2023
    Publication date: October 24, 2024
    Inventors: Kumar Abhishek, Neha Srivastava, Vivek Kumar Yadav, Sanjaykumar Hansrajbhai Kakasaniya, Vikram Joshi
  • Patent number: 12124309
    Abstract: A system-on-chip (SoC) having a switchable power domain capable of being placed in a standby mode during which a power supply of the switchable power domain is gated and having an always-on power domain. The always-on power domain includes an input sampling circuit, and the switchable power domain includes an input/output (IO) circuit configured to, during normal operation, receive data at a corresponding signal pin when an input buffer of the IO circuit is enabled, in which the corresponding signal pin is coupled to the input sampling circuit. The input sampling circuit is configured to, while the switchable power domain is entering the standby mode but before the power supply is gated, provide an override input enable signal to enable the input buffer of the IO circuit, sample an input bit value on the corresponding signal pin, and store the sampled bit value to provide an injection current fault indicator.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: October 22, 2024
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Subhashrahul Shekhar, Aditya Musunuri, Yi Zheng
  • Publication number: 20240289238
    Abstract: Disclosed is an improved approach to handle recovery failures associated with fatal recovery processes. A software crash is prevented when a program has a failure that would typically crash the software, involving analyzing the failure in an operation, accumulating the failure information, clearing the failure (hence preventing the immediate crash), and not performing the desired operation until the root cause of the failure is fixed.
    Type: Application
    Filed: February 28, 2023
    Publication date: August 29, 2024
    Applicant: Oracle International Corporation
    Inventors: Kishy Kumar, Ajay Paddayuru Shreepathi, Ajit Mylavarapu, Silvio Martinez, Guttu Sai Abhishek
  • Publication number: 20240220957
    Abstract: The present disclosure is directed to an artificial intelligence (AI) assisted monitoring system that uses cameras to recognize a product being moved by the user across the self-checkout unit and verifying whether the product was scanned at the point-of-sale terminal based on timestamp information associated with when the product was moved across the self-checkout unit to identify miss scan thefts.
    Type: Application
    Filed: May 2, 2023
    Publication date: July 4, 2024
    Inventors: Arun Patil, Ashok Jayasheela, Arun Vaishnav, Kumar Abhishek, Spoorti Nayak, Dharmavaram Arbaaz
  • Publication number: 20240211682
    Abstract: A method and system for generating and utilizing a personalized compression system includes receiving a first writing, extracting features from the first writing into hash values, generating a plurality of summaries for the first writing, each summary of the plurality of summaries having a different length, causing display of at least one summary of the plurality of summaries on a client, receiving, from a user of the client, an indication of a selection based on the displayed at least one of summary of the plurality of summaries, and refining the baseline machine learning model based on the hash values and the selected summary to generate a personalized machine learning model.
    Type: Application
    Filed: May 5, 2022
    Publication date: June 27, 2024
    Inventors: Titas De, Amartya CHAUDHURI, Kushal GHOSH, Kumar ABHISHEK
  • Publication number: 20240192745
    Abstract: Systems and methods for managing asynchronous resets in an SoC have been described. In an illustrative, non-limiting embodiment, a reset generation circuit in an SoC, may include a first reset generation circuit configured to enable a first reset signal based, at least in part, upon a clock signal and an indication to reset. The reset generation circuit may also include a second reset generation circuit coupled to the first reset generation circuit, in which the second reset generation circuit is configured to enable a second reset signal after the first reset signal is enabled. The first reset signal and the second reset signal are both provided to a component of the SoC.
    Type: Application
    Filed: May 11, 2023
    Publication date: June 13, 2024
    Inventors: Kumar Abhishek, Neha Srivastava, Yi Zheng, Nishant Kumar
  • Patent number: 11994888
    Abstract: A packaged die including a first and a second power supply pad configured to provide a first and a second power supply voltage, respectively, and circuitry powered by the first power supply voltage. A power pad handling circuitry includes a selectively enablable pull-down path coupled between the first power supply pad and the second power supply pad, a storage circuit configured to store a pull-down path enable bit, a clock input coupled to receive a boot clock, and an asynchronous input coupled to receive a power-on-reset (POR) signal. In response to assertion of the POR signal, the pull-down pat is enabled regardless of any signal received at the clock input and regardless the value of the pull-down path enable bit. When reset has completed, a value of the pull-down path enable bit is provided upon an active edge of the boot clock to selectively enable the pull-down path.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: May 28, 2024
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Sandeep Singh Jasrotia
  • Publication number: 20240160265
    Abstract: A system-on-chip (SoC) having a switchable power domain capable of being placed in a standby mode during which a power supply of the switchable power domain is gated and having an always-on power domain. The always-on power domain includes an input sampling circuit, and the switchable power domain includes an input/output (IO) circuit configured to, during normal operation, receive data at a corresponding signal pin when an input buffer of the IO circuit is enabled, in which the corresponding signal pin is coupled to the input sampling circuit. The input sampling circuit is configured to, while the switchable power domain is entering the standby mode but before the power supply is gated, provide an override input enable signal to enable the input buffer of the IO circuit, sample an input bit value on the corresponding signal pin, and store the sampled bit value to provide an injection current fault indicator.
    Type: Application
    Filed: November 16, 2022
    Publication date: May 16, 2024
    Inventors: Kumar Abhishek, Subhashrahul Shekhar, Aditya Musunuri, Yi Zheng
  • Patent number: 11961577
    Abstract: Analog-to-digital converters (ADCs) of an integrated circuit includes a first set of ADCs and second set of ADCs in which the ADCs of the first set are of a different type than the ADCs of the second set. On-chip testing of the ADCs includes calibrating an N-bit differential digital-to-analog converter (DAC) and storing a pair of calibration codes for each of 2N possible DAC input codes for the DAC in an on-chip memory. The first set of ADCs is tested using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC. Subsequently, the second set of ADCs is tested using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, in which M is less than N. During the testing of the second set of ADCs, a portion of the calibration codes stored in the on-chip memory is overwritten.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: April 16, 2024
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Xiankun Jin, Mark Lehmann
  • Publication number: 20240019883
    Abstract: A packaged die including a first and a second power supply pad configured to provide a first and a second power supply voltage, respectively, and circuitry powered by the first power supply voltage. A power pad handling circuitry includes a selectively enablable pull-down path coupled between the first power supply pad and the second power supply pad, a storage circuit configured to store a pull-down path enable bit, a clock input coupled to receive a boot clock, and an asynchronous input coupled to receive a power-on-reset (POR) signal. In response to assertion of the POR signal, the pull-down pat is enabled regardless of any signal received at the clock input and regardless the value of the pull-down path enable bit. When reset has completed, a value of the pull-down path enable bit is provided upon an active edge of the boot clock to selectively enable the pull-down path.
    Type: Application
    Filed: October 24, 2022
    Publication date: January 18, 2024
    Inventors: Kumar Abhishek, Sandeep Singh Jasrotia
  • Patent number: 11873138
    Abstract: A tamper evident package for secure delivery of a product is disclosed. The tamper evident packaging includes a plurality of sidewalls having a closure providing access to an interior compartment of the packaging. The closure includes a closure slide that urges a closure seal into cooperative engagement during movement of the closure slide. Cooperating ratchet teeth are provided in the closure slide and at a closed end of the closure to retain the closure slide in a locked position. The closure slide includes a land for carrying a unique identifier code. The unique identifier code is visible through a window in the closure when the closure slide is in the locked position. The tamper evident packaging may be used with a product delivery service where the unique identifier code is used to identify an order through a packing of the product through receipt of the product by the customer.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: January 16, 2024
    Inventors: Robert Allen Epstein, Kumar Abhishek, Walter Vittitoe, Tia Vittitoe
  • Publication number: 20240013848
    Abstract: Analog-to-digital converters (ADCs) of an integrated circuit includes a first set of ADCs and second set of ADCs in which the ADCs of the first set are of a different type than the ADCs of the second set. On-chip testing of the ADCs includes calibrating an N-bit differential digital-to-analog converter (DAC) and storing a pair of calibration codes for each of 2N possible DAC input codes for the DAC in an on-chip memory. The first set of ADCs is tested using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC. Subsequently, the second set of ADCs is tested using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, in which M is less than N. During the testing of the second set of ADCs, a portion of the calibration codes stored in the on-chip memory is overwritten.
    Type: Application
    Filed: July 5, 2022
    Publication date: January 11, 2024
    Inventors: Kumar Abhishek, Xiankun Jin, Mark Lehmann
  • Publication number: 20230296468
    Abstract: The present invention discloses a dual mode fuel tank leakage detector (100), comprising of an electromechanical valve (1) with a canister port, an engine control unit, pump assembly, a sensor (3) and works in pressure condition by comparing a measured pressure with reference pressure; in case there is leakage then the pressure is not upto the reference pressure within time interval. In case of no leakage, the pressure will be equal/above than the reference pressure, the leakage detector (100) works in vacuum condition by comparing a measured leakage with a reference leakage, in case there is a leakage the measured vacuum is not able to reach to the reference vacuum within a time interval and when there is no leakage, the measured vacuum will be equal or above from the reference vacuum and fuel tank leakage detector (100) enables to monitor leakage detection either in vacuum or pressure conditions.
    Type: Application
    Filed: March 17, 2022
    Publication date: September 21, 2023
    Inventors: KABIR BHANDARI, AMARDIP KUMAR, KUMAR ABHISHEK, ABHIJATYA GUPTA
  • Publication number: 20230232017
    Abstract: In non-limiting examples of the present disclosure, systems, methods and devices for determining image compression optimums are provided. An image may be processed with a machine learning model that has been trained to identify object types in digital images. A first object and a first object type of the first object may be identified in the image. A first compressed version of the image may be generated, wherein the first compressed version has a first storage size. The first object and the first object type of the first object may be identified in the first compressed version of the image. A second compressed version of the image may be generated based on the identification of the first object and the first object type in the first compressed version of the image. The second compressed version may have a smaller storage size than the first storage size.
    Type: Application
    Filed: April 22, 2021
    Publication date: July 20, 2023
    Inventors: Titas DE, Saurabh UTTAM, Saurabh CHAWLA, Kumar ABHISHEK, Bhavatarini MALLIKARJUNA PUSHPA, Sourabh CHAKI
  • Publication number: 20230112748
    Abstract: The present invention relates to an oil control solenoid valve with improved pressure balance for high pressure applications and a method of assembling thereof. More particularly, the present invention provides an oil control solenoid valve (101) with a pressure balance assembly comprising of a fixed sleeve (2) with at least one inlet and one outlet, a movable plunger (1) having two ends and at least one bush (3) and the method of assembling thereof thus providing the pressure balance at both the ends of the plunger (1).
    Type: Application
    Filed: February 12, 2021
    Publication date: April 13, 2023
    Inventors: KABIR BHANDARI, AMARDIP KUMAR, KUMAR ABHISHEK, SUDHIR PATTNAIK
  • Publication number: 20230100007
    Abstract: The present invention relates to a system for monitoring plunger movement in non-energized condition in real time. More particularly, the present invention relates to a system comprising a plunger, a locking pin, a permanent magnet and a multi-point sensor to measure the position of plunger in a non-energized condition and to improve the automatic shut off or start on the pump.
    Type: Application
    Filed: February 12, 2021
    Publication date: March 30, 2023
    Inventors: KABIR BHANDARI, AMARDIP KUMAR, KUMAR ABHISHEK, SUDHIR PATTNAIK
  • Publication number: 20230078232
    Abstract: The present invention provides a system to detect real time plunger position in oil solenoid valve. More particularly, the present invention provides a position sensor embedded in the oil solenoid valve for detecting a plunger position in real time by downward movement of the plunger and having application in automobile for cooling of turbocharger.
    Type: Application
    Filed: February 15, 2021
    Publication date: March 16, 2023
    Inventors: KABIR BHANDARI, AMARDIP KUMAR, KUMAR ABHISHEK, SUDHIR PATTNAIK
  • Publication number: 20230033973
    Abstract: A low voltage differential signaling (LVDS) receiver includes a receiver circuit including first and second inputs coupled to first and second conductive pads, respectively, and an output coupled to an input of a digital controller, and a dummy transmitter circuit including a first input coupled to receive a common mode voltage (VCM) tune signal, a second input coupled to a loopback input signal, a third input coupled to a loopback enable signal, a first output coupled to the first input of the receiver circuit, and a second output coupled to the second input of the receiver circuit. When a test mode of operation is enabled, the digital controller asserts the loopback enable signal, and the dummy transmitter circuit generates a pair of test differential signals based on the VCM tune signal, wherein the VCM tune signal varies to test the LVDS receiver over a range of common mode voltages.
    Type: Application
    Filed: July 20, 2022
    Publication date: February 2, 2023
    Inventors: Kumar Abhishek, Srikanth Jagannathan, Frederic Benoist
  • Patent number: 11561255
    Abstract: An integrated circuit includes an input/output (I/O) circuit configured to receive a first signal and a second signal and a fault detection circuit. The I/O circuit includes an I/O terminal, an I/O buffer, and a pull resistor having a first terminal coupled to the I/O terminal. The fault detection circuit is configured to determine whether a predetermined number of toggles of the first signal occurs while the second signal is held at a constant logic state, assert a fault indicator when the predetermined number of toggles occurs, and negate the fault indicator when the predetermined number of toggles does not occur.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: January 24, 2023
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Xiankun Jin, Srikanth Jagannathan
  • Patent number: 11545407
    Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Kumar Abhishek Singh, Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Manish Dubey, Ravindranath Mahajan, Ram Viswanath, James C. Matayabas, Jr.