Patents by Inventor Kumar Abhishek

Kumar Abhishek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230100007
    Abstract: The present invention relates to a system for monitoring plunger movement in non-energized condition in real time. More particularly, the present invention relates to a system comprising a plunger, a locking pin, a permanent magnet and a multi-point sensor to measure the position of plunger in a non-energized condition and to improve the automatic shut off or start on the pump.
    Type: Application
    Filed: February 12, 2021
    Publication date: March 30, 2023
    Inventors: KABIR BHANDARI, AMARDIP KUMAR, KUMAR ABHISHEK, SUDHIR PATTNAIK
  • Publication number: 20230078232
    Abstract: The present invention provides a system to detect real time plunger position in oil solenoid valve. More particularly, the present invention provides a position sensor embedded in the oil solenoid valve for detecting a plunger position in real time by downward movement of the plunger and having application in automobile for cooling of turbocharger.
    Type: Application
    Filed: February 15, 2021
    Publication date: March 16, 2023
    Inventors: KABIR BHANDARI, AMARDIP KUMAR, KUMAR ABHISHEK, SUDHIR PATTNAIK
  • Publication number: 20230033973
    Abstract: A low voltage differential signaling (LVDS) receiver includes a receiver circuit including first and second inputs coupled to first and second conductive pads, respectively, and an output coupled to an input of a digital controller, and a dummy transmitter circuit including a first input coupled to receive a common mode voltage (VCM) tune signal, a second input coupled to a loopback input signal, a third input coupled to a loopback enable signal, a first output coupled to the first input of the receiver circuit, and a second output coupled to the second input of the receiver circuit. When a test mode of operation is enabled, the digital controller asserts the loopback enable signal, and the dummy transmitter circuit generates a pair of test differential signals based on the VCM tune signal, wherein the VCM tune signal varies to test the LVDS receiver over a range of common mode voltages.
    Type: Application
    Filed: July 20, 2022
    Publication date: February 2, 2023
    Inventors: Kumar Abhishek, Srikanth Jagannathan, Frederic Benoist
  • Patent number: 11561255
    Abstract: An integrated circuit includes an input/output (I/O) circuit configured to receive a first signal and a second signal and a fault detection circuit. The I/O circuit includes an I/O terminal, an I/O buffer, and a pull resistor having a first terminal coupled to the I/O terminal. The fault detection circuit is configured to determine whether a predetermined number of toggles of the first signal occurs while the second signal is held at a constant logic state, assert a fault indicator when the predetermined number of toggles occurs, and negate the fault indicator when the predetermined number of toggles does not occur.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: January 24, 2023
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Xiankun Jin, Srikanth Jagannathan
  • Patent number: 11545407
    Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Kumar Abhishek Singh, Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Manish Dubey, Ravindranath Mahajan, Ram Viswanath, James C. Matayabas, Jr.
  • Publication number: 20220390694
    Abstract: The removal of heat from silicon photonic integrated circuit devices is a significant issue in integrated circuit packages. As presented herein, the removal of heat may be facilitated with an optically compatible thermal interface structure on the silicon photonic integrated circuit device. These thermal interface structures may include stack-up designs, comprising an optical isolation structure and a thermal interface material, which reduces light coupling effects, while effectively conducting heat from the silicon photonic integrated circuit device to a heat dissipation device, thereby allowing effective management of the temperature of the silicon photonic integrated circuit device.
    Type: Application
    Filed: June 4, 2021
    Publication date: December 8, 2022
    Applicant: Intel Corporation
    Inventors: Chia-Pin Chiu, Kaveh Hosseini, Thu Ngoc Tran, Yew Fatt Kok, Kumar Abhishek Singh, Xiaoqian Li, Marely Tejeda Ferrari, Ravindranath Mahajan, Kevin Ma, Casey Thielen
  • Patent number: 11519960
    Abstract: An integrated circuit device includes general purpose input/output (I/O) circuitry having a transmit level shifter circuit in a transmit I/O circuit and a receive level shifter circuit in a receive I/O circuit. The integrated circuit device also includes an I/O pad which couples an output of the transmit level shifter circuit to an input of the receive level shifter circuit, a counter circuit, an inverter circuit coupled between the receive level shifter circuit and the counter circuit, and a logic gate. The logic gate includes a first input coupled to an output of the inverter circuit, a second input coupled to a counter_done signal from the counter circuit, and an output coupled to provide a data_out signal to an input of the transmit level shifter circuit.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: December 6, 2022
    Assignee: NXP USA, Inc.
    Inventors: Srikanth Jagannathan, Kumar Abhishek, Gayathri Bhagavatheeswaran
  • Publication number: 20220366293
    Abstract: An approach is provided for augmenting text of a small class for text classification. An imbalanced dataset is received. A small class is identified. The small class includes initial text records in the imbalanced dataset. A balanced dataset is generated from the imbalanced dataset by augmenting the initial text records by using weighted word scores indicating respective measures of importance of words in classes in the imbalanced dataset. The balanced dataset is sent to a supervised machine learning model. The supervised machine learning model is trained on the balanced dataset. Using the supervised machine learning model which employs the augmented initial text records, a text classification of a new dataset is performed. The domain of the new dataset matches the domain of the imbalanced dataset.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 17, 2022
    Inventor: Kumar Abhishek
  • Publication number: 20220368338
    Abstract: An integrated circuit device includes a digital sine wave generator configured to produce portions of a digital sine wave, a combiner circuit configured to output each of the portions of the digital sine wave combined with a respective calibration code during operation in a post-production dynamic test mode, a digital to analog converter (DAC) configured to output an analog sine wave based on the output of the combiner circuit, and a test analog to digital converter (ADC) including an input terminal directly connected to the output of the DAC, and configured to generate a second digital sine wave based on the analog sine wave.
    Type: Application
    Filed: May 11, 2021
    Publication date: November 17, 2022
    Inventors: Xiankun Jin, Douglas Alan Garrity, Mark Lehmann, Kumar Abhishek
  • Patent number: 11489535
    Abstract: Body text indent—does not have paragraph numbering turned on. Not needed in the Abstract. An integrated circuit device includes a digital sine wave generator configured to produce portions of a digital sine wave, a combiner circuit configured to output each of the portions of the digital sine wave combined with a respective calibration code during operation in a post-production dynamic test mode, a digital to analog converter (DAC) configured to output an analog sine wave based on the output of the combiner circuit, and a test analog to digital converter (ADC) including an input terminal directly connected to the output of the DAC, and configured to generate a second digital sine wave based on the analog sine wave.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: November 1, 2022
    Assignee: NXP B.V.
    Inventors: Xiankun Jin, Douglas Alan Garrity, Mark Lehmann, Kumar Abhishek
  • Publication number: 20220334176
    Abstract: An integrated circuit includes an input/output (I/O) circuit configured to receive a first signal and a second signal and a fault detection circuit. The I/O circuit includes an I/O terminal, an I/O buffer, and a pull resistor having a first terminal coupled to the I/O terminal. The fault detection circuit is configured to determine whether a predetermined number of toggles of the first signal occurs while the second signal is held at a constant logic state, assert a fault indicator when the predetermined number of toggles occurs, and negate the fault indicator when the predetermined number of toggles does not occur.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 20, 2022
    Inventors: Kumar Abhishek, Xiankun Jin, Srikanth Jagannathan
  • Patent number: 11462527
    Abstract: Embodiments disclosed herein include an electronics package. In an embodiment, the electronics package comprises a package substrate and a die on the package substrate. In an embodiment, a mold layer is positioned over the package substrate. In an embodiment, the electronics package further comprises through-mold interconnects through the mold layer, and a trench that extends at least partially into the mold layer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventors: Kumar Abhishek Singh, Zhaozhi Li, Thomas J. Debonis, Robert Nickerson, Rees Winters
  • Publication number: 20220291076
    Abstract: The present invention relates to leakage detection unit (100) comprise of an upper housing (5), a lower housing (6) accommodating an electromechanical valve (1), a pump assembly (2), a pressure sensor (3) and a bush (4), wherein the pump assembly (2) includes a pump that permits flow of air that, due to which pressure in passage of the pump becomes constant after a time interval and that pressure is considered as reference pressure. The pressure is measured by help of the pressure sensor (3) and in case the measured pressure is not equal or above to the reference pressure than there is leakage in the isolation valve (100), whereas in case the measured pressure is equal or above the reference pressure that there is no leakage or some permissible amount of leakage in the fuel tank within the time interval.
    Type: Application
    Filed: March 15, 2022
    Publication date: September 15, 2022
    Inventors: KABIR BHANDARI, AMARDIP KUMAR, KUMAR ABHISHEK, ABHIJATYA GUPTA
  • Publication number: 20220252059
    Abstract: The present invention relates to an improved rubber sealed plunger assembly of electrical compressor by-pass valve. The present invention relates to an improved rubber sealed plunger assembly of electrical compressor by-pass valve with lip seal design to eliminate its over molding and improve performances like leakage and response time. The present invention provides an improved rubber sealed plunger assembly comprising of components including but not limited to a rubber disk cover, a rubber disk, a plunger body, a diaphragm and a diaphragm holder.
    Type: Application
    Filed: July 18, 2020
    Publication date: August 11, 2022
    Inventors: KABIR BHANDARI, AMARDIP KUMAR, KUMAR ABHISHEK, PARSURAM ROUT
  • Publication number: 20220057448
    Abstract: An integrated circuit device includes general purpose input/output (I/O) circuitry having a transmit level shifter circuit in a transmit I/O circuit and a receive level shifter circuit in a receive I/O circuit. The integrated circuit device also includes an I/O pad which couples an output of the transmit level shifter circuit to an input of the receive level shifter circuit, a counter circuit, an inverter circuit coupled between the receive level shifter circuit and the counter circuit, and a logic gate. The logic gate includes a first input coupled to an output of the inverter circuit, a second input coupled to a counter_done signal from the counter circuit, and an output coupled to provide a data_out signal to an input of the transmit level shifter circuit.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 24, 2022
    Inventors: Srikanth Jagannathan, Kumar Abhishek, Gayathri Bhagavatheeswaran
  • Patent number: 11196411
    Abstract: A circuit including a device including a first and second node. The device operating in at least an enabled mode and a disabled mode. The circuit including a voltage control circuit. The voltage control circuit including a current source for sourcing current to or sinking current from the first node during the disabled mode and a voltage difference detector including an output for providing an indication of a measured voltage difference between the first node and the second node. The voltage control circuit includes a current source control circuit including a first input to receive the indication of the measured voltage difference and an output to control current sourced to or sinked from the first node by the current source to limit a voltage difference between the first and second node based on a comparison between the indication of the measured voltage difference and an indication of a target voltage difference.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: December 7, 2021
    Assignee: NXP USA, Inc.
    Inventors: Srikanth Jagannathan, Kumar Abhishek
  • Patent number: 11146057
    Abstract: An integrated circuit includes a signal pad, an output buffer having an output coupled to the signal pad and having an enable input, an input buffer having an input coupled to the signal pad and having an enable input, a counter, and a gating circuit. The counter is enabled to start counting down a predetermined count value when a voltage on the signal pad is both higher than a predetermined low threshold voltage and lower than a predetermined high threshold voltage, wherein the predetermined low threshold voltage corresponds to a threshold below which a voltage corresponds to a logic level zero and the predetermined high threshold voltage corresponds to a threshold above which a voltage corresponds to a logic level one. The gating circuit is configured to, in response to the counter expiring, disable the input buffer and the output buffer.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: October 12, 2021
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Srikanth Jagannathan
  • Publication number: 20210284395
    Abstract: A tamper evident package for secure delivery of a product is disclosed. The tamper evident packaging includes a plurality of sidewalls having a closure providing access to an interior compartment of the packaging. The closure includes a closure slide that urges a closure seal into cooperative engagement during movement of the closure slide. Cooperating ratchet teeth are provided in the closure slide and at a closed end of the closure to retain the closure slide in a locked position. The closure slide includes a land for carrying a unique identifier code. The unique identifier code is visible through a window in the closure when the closure slide is in the locked position. The tamper evident packaging may be used with a product delivery service where the unique identifier code is used to identify an order through a packing of the product through receipt of the product by the customer.
    Type: Application
    Filed: March 15, 2021
    Publication date: September 16, 2021
    Applicant: Safeplate LLC
    Inventors: Robert Allen Epstein, Kumar Abhishek, Walter Vittitoe, Tia Vittitoe
  • Patent number: 11099231
    Abstract: A current leg located in a voltage domain where the current leg includes a transistor of a current mirror having a maximum voltage rating of less than the voltage of the voltage domain. The current leg includes a resistive element circuit to provide a first resistance during a normal mode of operation of the current leg and a different resistance during of a stress test of the transistor in a test mode of the circuit.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: August 24, 2021
    Assignee: NXP USA, INC.
    Inventors: Srikanth Jagannathan, Kumar Abhishek
  • Publication number: 20210239232
    Abstract: The present invention provides a blow-off valve for an internal combustion engine. More specifically, the invention provides a blow-off valve with dual axis internal seal ring that works in axial and radial direction to improve the leakage while reducing the child parts of assembly. The blow-off valve provided comprises of a plunger body, a compression spring, a moving core, a two axis internal seal ring, a fix core, a bobbin, coil, coil housing, a plunger housing and terminals to power up the coil.
    Type: Application
    Filed: June 10, 2019
    Publication date: August 5, 2021
    Inventors: KABIR BHANDARI, AMARDIP KUMAR, KUMAR ABHISHEK, PARSURAM ROUT