Patents by Inventor Kumar Abhishek

Kumar Abhishek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10581532
    Abstract: The various embodiments of the present invention disclose a system and method for initiating communication between different devices using audio frequency. The invention enables buzzers to generate monotone or limited tones for communication and data transmission. The first electronic device includes a frequency generator, an audio driver library, the buzzer or speaker, and a transmitter & the second electronic includes has an audio receiver mic, audio driver library, frequency receiver. The transmitter generates a communication request from a first electronic device to second electronic device. Further, the first electronic device and the second electronic device is installed with a buzzer application which when executed on the processor, causes the processor to enable communication between the first electronic device and the second electronic device by generating audible frequency using the buzzer/speaker.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: March 3, 2020
    Assignee: NAFFA INNOVATIONS PRIVATE LIMTIED
    Inventors: Kumar Abhishek, Ibrahim Sankadal, Sidaray Biradar
  • Patent number: 10560207
    Abstract: A method for facilitating targeted secondary content delivery to a user is envisaged. The primary content is broadcast on a television accessible to a user, followed by targeted delivery of relevant secondary content onto a handheld device of the user. The secondary content deemed as being relevant to the primary content is delivered in an unobtrusive manner without altering the viewing experience of the primary content, only after verification of the viewership of the primary content. The secondary content deemed as relevant to the primary content is transmitted to a handheld device accessible to the user thereby not altering the viewing experience corresponding to the viewing of the primary content on the television. The secondary content is delivered to the handheld device via electromagnetic waves, preferably radio waves without necessitating an active internet connection for the handheld device, and without necessitating the user to remain logged-on to the handheld device.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: February 11, 2020
    Assignee: NAFFA INNOVATIONS PRIVATE LIMITED
    Inventors: Kumar Abhishek, Ibrahim Sankadal, Nishant Pashine
  • Publication number: 20200035658
    Abstract: Embodiments disclosed herein include an electronics package. In an embodiment, the electronics package comprises a package substrate and a die on the package substrate. In an embodiment, a mold layer is positioned over the package substrate. In an embodiment, the electronics package further comprises through-mold interconnects through the mold layer, and a trench that extends at least partially into the mold layer.
    Type: Application
    Filed: July 30, 2018
    Publication date: January 30, 2020
    Inventors: Kumar Abhishek SINGH, Zhaozhi LI, Thomas J. DEBONIS, Robert NICKERSON, Rees WINTERS
  • Publication number: 20190288654
    Abstract: An amplifier includes a differential input stage, a hysteresis stage, coupled to the differential input stage, a cascode stage coupled to the hysteresis stage, a feedback stage coupled to an output of the cascode stage and configured to provide a feedback signal to the hysteresis stage, and an output stage coupled to the output of the cascode stage. The output stage includes a hysteresis inverter coupled between the output of the cascode stage and the amplifier output.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 19, 2019
    Inventors: KUMAR ABHISHEK, Srikanth Jagannathan
  • Patent number: 10418952
    Abstract: An amplifier includes a differential input stage, a hysteresis stage, coupled to the differential input stage, a cascode stage coupled to the hysteresis stage, a feedback stage coupled to an output of the cascode stage and configured to provide a feedback signal to the hysteresis stage, and an output stage coupled to the output of the cascode stage. The output stage includes a hysteresis inverter coupled between the output of the cascode stage and the amplifier output.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: September 17, 2019
    Assignee: NXP USA, INC.
    Inventors: Kumar Abhishek, Srikanth Jagannathan
  • Publication number: 20190229822
    Abstract: A method for facilitating targeted secondary content delivery to a user is envisaged. The primary content is broadcast on a television accessible to a user, followed by targeted delivery of relevant secondary content onto a handheld device of the user. The secondary content deemed as being relevant to the primary content is delivered in an unobtrusive manner without altering the viewing experience of the primary content, only after verification of the viewership of the primary content. The secondary content deemed as relevant to the primary content is transmitted to a handheld device accessible to the user thereby not altering the viewing experience corresponding to the viewing of the primary content on the television. The secondary content is delivered to the handheld device via electromagnetic waves, preferably radio waves without necessitating an active internet connection for the handheld device, and without necessitating the user to remain logged-on to the handheld device.
    Type: Application
    Filed: August 10, 2017
    Publication date: July 25, 2019
    Inventors: KUMAR ABHISHEK, IBRAHIM SANKADAL, NISHANT PASHINE
  • Patent number: 10361732
    Abstract: An integrated circuit includes a transmitter having a data input coupled to receive a single-ended data signal, a reference input coupled to receive a bandgap reference, a first differential output, and a second differential output. The transmitter is configured to, during normal operation, convert the single-ended data signal at the data input into a first differential signal at the first differential output and a second differential signal at the second differential output in which the first differential signal and the second differential signal are complementary to each other. A fault detection circuit is coupled to the first and second differential outputs and is configured to detect a load short fault condition and a bandgap short condition based on the first and second differential signals at the first and second differential outputs while forcing the data input to zero.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: July 23, 2019
    Assignee: NXP USA, Inc.
    Inventors: Srikanth Jagannathan, Kumar Abhishek
  • Patent number: 10312929
    Abstract: The embodiments described herein provide analog-to-digital converters and methods that can reduce the likelihood of excessive voltage drop during the conversion of weakly driven signals while still providing the ability to perform an accurate analog-to-digital conversion. In general, the embodiments described herein reduce the likelihood of excessive voltage drop during the conversion of weakly driven signals by pre-charging the sampling capacitor used in the conversion. For example, the embodiments can apply the buffered input signal apply to the sampling capacitor for a first sampling cycle to pre-charge the sampling capacitor, and then directly apply the unbuffered input signal to the sampling capacitor for a second sampling cycle to final-charge the sampling capacitor. With the sampling capacitor charged using the two stage charging, a digital output corresponding to the charge of the sampling capacitor is generated.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: June 4, 2019
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Srikanth Jagannathan, Shanaka Pradeep Yapa Appuhamillage Don
  • Patent number: 10242955
    Abstract: An active tamper detection circuit with bypass detection is provided. A bypass detection circuit is coupled to an active mesh loop. The bypass detector includes a voltage comparator with a variable hysteresis control circuit and a calibration engine. The bypass detector detects a change in impedance in the mesh when an attacker attempts to bypass the active loop using a wire. As part of a boot-up sequence, the calibration engine runs a hysteresis sweep on the voltage comparator and stores a hysteresis sweep boot-up signature. When bypass protection is enabled, the bypass detector runs a hysteresis sweep of the voltage comparator periodically at a predetermined interval. Each sweep generates a generated signature that is compared to the stored boot-up signature. Any signature mismatch will be signaled as an impedance mismatch, or tamper. The hysteresis step size is also programmable. The calibration engine can make small changes to the boot-up signature to allow for small voltage variations.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 26, 2019
    Assignee: NXP USA, Inc.
    Inventors: Mohit Arora, Kumar Abhishek, Prashant Bhargava, Rakesh Pandey
  • Patent number: 10205441
    Abstract: A level shifter includes a level shifting circuit, a variable bias voltage generator, and a bias voltage generator controller. The level shifting circuit is configured to level shift an input signal at a first voltage level to an output signal having a second voltage level. The second voltage level is higher than the first voltage level. The level shifting circuit includes a current mirror, an input circuit for receiving the differential input signals, and a coupling circuit for coupling the current mirror to the input circuit in response to a variable bias voltage. The variable bias voltage generator is configured to provide the variable bias voltage at one of a plurality of voltage levels. The bias voltage generator controller provides a select signal to select the voltage level from the plurality of voltage levels in response to measuring the duty cycle of the output signal to maintain the duty cycle of the output signal at a predetermined duty cycle.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 12, 2019
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Srikanth Jagannathan
  • Patent number: 10191110
    Abstract: An integrated circuit and a method of self-testing the integrated circuit are provided. The method comprises: generating a reference voltage at an output of a reference circuit; initiating a test of the reference circuit during a test mode; determining whether the test of the reference circuit passes; and comparing, if the test of the reference circuit passes, a first voltage with the reference voltage. The disclosed test method provides for more complete testing of the integrated circuit.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: January 29, 2019
    Assignee: NXP USA, INC.
    Inventors: Kumar Abhishek, Regis Gubian, Sakshi Gupta, Sunny Gupta, Kushal Kamal
  • Publication number: 20190028208
    Abstract: The various embodiments of the present invention disclose a system and method for initiating communication between different devices using audio frequency. The invention enables buzzers to generate monotone or limited tones for communication and data transmission. The first electronic device includes a frequency generator, an audio driver library, the buzzer or speaker, and a transmitter & the second electronic includes has an audio receiver mic, audio driver library, frequency receiver. The transmitter generates a communication request from a first electronic device to second electronic device. Further, the first electronic device and the second electronic device is installed with a buzzer application which when executed on the processor, causes the processor to enable communication between the first electronic device and the second electronic device by generating audible frequency using the buzzer/speaker.
    Type: Application
    Filed: July 23, 2018
    Publication date: January 24, 2019
    Inventors: Kumar ABHISHEK, Ibrahim SANKADAL, Sidaray BIRADAR
  • Patent number: 10157087
    Abstract: A clock generator circuit includes an internal reference clock generator, a sequential circuit, and a pulse generator circuit. The internal reference clock generator circuit receives a clock buffer signal, a reset signal, and provides a first clock signal. The sequential circuit receives the first clock signal, and provides an internal reference clock signal based on the first clock signal. The pulse generator circuit receives the internal reference clock signal, a slow ring oscillator clock signal, and the reset signal. The pulse generator circuit counts a number of internal reference clock signals cycles for each cycle of the slow ring oscillator clock signal, and generates a pulse signal in response to the number being equal to zero during a cycle of the slow ring oscillator clock signal. The pulse signal toggles the flip-flop clock circuit to recover from a deadlock.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: December 18, 2018
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Srikanth Jagannathan
  • Patent number: 10153768
    Abstract: Input/output circuitry includes a first PMOS device and a first NMOS device having first current electrodes are connected to each other and a pad. First selection circuitry, when the I/O circuitry is disabled, provides a first supply voltage to a control electrode and an N-well of the first PMOS device when the pad voltage is between the first and second supply voltages and to directly provide the pad voltage to the control electrode and the N-well of the first PMOS device when the pad voltage is greater than the first supply voltage. Similarly, second selection circuitry, when the I/O circuitry is disabled, provides a second supply voltage or directly provides the pad voltage to a control electrode and a P-well of the first NMOS device depending on whether the pad voltage is between the first and second supply voltages or less than the second supply voltage, respectively.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 11, 2018
    Assignee: NXP USA, Inc.
    Inventors: Christopher James Micielli, Srikanth Jagannathan, Hector Sanchez, Kumar Abhishek
  • Patent number: 10148261
    Abstract: A low voltage differential signaling (LVDS) driver circuit, system, apparatus, and methodology are provided for controlling switching components in a primary current stage and a pre-emphasis current stage with an adaptive pre-emphasis gain tuning hardware control circuit arranged to provide control signals for periodically tuning a pre-emphasis gain setting for the secondary pre-emphasis current stage by selecting an optimum pre-emphasis gain setting from a plurality of pre-emphasis gain setting which minimizes an inter-symbol interference (ISI) jitter measure for the LVDS driver circuit.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: December 4, 2018
    Assignee: NXP USA, Inc.
    Inventors: Srikanth Jagannathan, Kumar Abhishek
  • Publication number: 20180225655
    Abstract: The embodiments herein provide a method and system for establishing data communication through a secure channel using audio signals. The method comprises registering a plurality of users to an application, initiating the application by a registered user, emitting audio signals using the audio signal emitter to establish a secure channel with the other participating device, receiving audio signals from the other participating device, validating the other participating device using a validating module, detecting the proximity of the other participating device using a proximity detector, establishing a secure channel between the participating devices, wherein the secure channel is established using audio channels, and enabling financial transaction between the participating devices.
    Type: Application
    Filed: October 27, 2015
    Publication date: August 9, 2018
    Inventor: KUMAR ABHISHEK
  • Patent number: 10013042
    Abstract: A memory system includes a core power supply node configured to provide a core power supply; backup regulator configured to provide a backup power supply; memory configured to be powered by the core power supply or the backup power supply; threshold detection circuitry configured to provide a first indicator that when asserted indicates the core power supply has fallen to a first threshold, a second indicator that when asserted indicates the core power supply has fallen to a second threshold, and a third indicator that when asserted indicates the core power supply has fallen to a third threshold. The memory system also includes power sequence detection circuitry is configured to determine, upon the core power supply falling and based on which of the first, second, and third indicators are asserted, whether the asserted indicators have been asserted in a correct sequence and provide a first test result accordingly.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: July 3, 2018
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Srikanth Jagannathan
  • Publication number: 20180061780
    Abstract: An active tamper detection circuit with bypass detection is provided. A bypass detection circuit is coupled to an active mesh loop. The bypass detector includes a voltage comparator with a variable hysteresis control circuit and a calibration engine. The bypass detector detects a change in impedance in the mesh when an attacker attempts to bypass the active loop using a wire. As part of a boot-up sequence, the calibration engine runs a hysteresis sweep on the voltage comparator and stores a hysteresis sweep boot-up signature. When bypass protection is enabled, the bypass detector runs a hysteresis sweep of the voltage comparator periodically at a predetermined interval. Each sweep generates a generated signature that is compared to the stored boot-up signature. Any signature mismatch will be signaled as an impedance mismatch, or tamper. The hysteresis step size is also programmable. The calibration engine can make small changes to the boot-up signature to allow for small voltage variations.
    Type: Application
    Filed: August 29, 2016
    Publication date: March 1, 2018
    Inventors: MOHIT ARORA, KUMAR ABHISHEK, PRASHANT BHARGAVA, RAKESH PANDEY
  • Patent number: 9697065
    Abstract: A method for managing a reset process in a processing system is provided. The method includes enabling a watch dog unit based on a power-on reset (POR) event. A stuck in reset condition indication is received at the watch dog unit and used to determine whether the received reset condition indication corresponds to an unintentional reset condition. If the received reset condition indication is an indication of an unintentional reset condition, a watch dog POR trigger signal is generated and a reset state machine is repeated for system recovery.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: July 4, 2017
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Steven K. Watkins, Garima Sharda, James M. Giandelone, Stefano Pietri, Thomas H. Luedeke
  • Publication number: 20170169516
    Abstract: Methods and systems for automatically analyzing financial/corporate information and reporting it in form of media. Embodiments disclosed herein relate to analysis and reporting of financial performance and related items and more particularly to analysis and reporting of financial performance and related items of portfolio(s)/organization(s) in the form of media.
    Type: Application
    Filed: September 22, 2016
    Publication date: June 15, 2017
    Applicant: Amigobulls Inc.
    Inventors: Chandrashekhar Arwind Sohoni, Mandeep Makkar, Harish Kumar, Kumar Abhishek