Patents by Inventor Kumar Jain

Kumar Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12118546
    Abstract: Machine learning techniques are disclosed for rebuilding transactions to predict cash position. In one aspect a method includes obtaining data for an original transaction, classifying the original transaction into a class of multiple classes based on the data, predicting first tranche delay days for the original transaction based on the class and the data, predicting a tranche count for the original transaction based on the class and the data, predicting a tranche interval for the original transaction based on the class and the data; and rebuilding the original transaction as one or more future transactions based on the class, the first tranche delay days, the tranche count, and tranche interval. Each of the one or more future transactions comprise an updated amount of the original transaction, an updated date upon which the original transaction is anticipated, or both.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: October 15, 2024
    Assignee: ORACLE FINANCIAL SERVICES SOFTWARE LIMITED
    Inventors: Mridul Kumar Nath, Prajwal Patil, Rupa Satyabodha Kolhar, Anshul Kumar Jain
  • Publication number: 20240339141
    Abstract: Devices, circuits, and methods are provided. A circuit comprises a tracking word line circuit that is configured to receive an internal clock signal, a turbo signal, and a read enable signal, and to generate a first tracking reading signal and a first tracking writing signal in response to the internal clock signal the turbo signal, and the write enable signal. The circuit also comprises a tracking bit line circuit configured to receive the first tracking reading signal and the first tracking writing signal, wherein the tracking bit line circuit is configured to generate a tracking bit line signal in response to the first tracking reading signal and the first tracking writing signal, wherein the tracking word line circuit is configured to generate a reset signal in response to the tracking bit line signal and transmit the reset signal to the clock generator.
    Type: Application
    Filed: June 13, 2023
    Publication date: October 10, 2024
    Inventors: Sanjeev Kumar Jain, Atul Katoch
  • Publication number: 20240339140
    Abstract: The present disclosure provides a memory device, which includes a memory array, a read-clock generation circuit, and a local input/output circuit. The read-clock generation circuit receives a sense amplifier enable signal, a first sense amplifier pre-charge signal, and a latched write enable signal to generate a first read enable signal. The local input/output circuit includes multiple pairs of column-address pass gates, and a pair of read pass gates. The plurality of pairs of column-address pass gates are configured to receive data from a bit-line pair of the memory cells in a row selected by an address signal. The pair of read pass gates connects a read bit-line pair to the bit-line pair in response to the first read enable signal being in a low-logic state. The first read enable signal is de-asserted after the read bit-line pair connected to the pair of read pass gates are pre-charged.
    Type: Application
    Filed: April 7, 2023
    Publication date: October 10, 2024
    Inventors: SANJEEV KUMAR JAIN, ATUL KATOCH
  • Patent number: 12111795
    Abstract: A method for managing replication of cloned files is provided. Embodiments include determining, at a source system, that a first file has been cloned to create a second file. Embodiments include sending, from the source system to a replica system, an address of the first extent and an indication that a status of the first extent has changed from non-cloned to cloned. Embodiments include changing, at the replica system, a status of a second extent associated with a replica of the first file on the replica system from non-cloned to cloned and creating a mapping of the address of the first extent to an address of the second extent on the replica system. Embodiments include creating, at the replica system, a replica of the second file comprising a reference to the address of the second extent on the replica system.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: October 8, 2024
    Assignee: VMware LLC
    Inventors: Abhay Kumar Jain, Sriram Patil, Junlong Gao, Wenguang Wang
  • Publication number: 20240329885
    Abstract: Methods, systems, and devices related to signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may also include a controller configured to determine whether data associated with an address of the memory array is stored in one or more cache blocks of the signal development cache. As an example, the memory device may determine whether the data is stored in one or more cache blocks of the signal development cache based on mapping information associated with the address of the memory array.
    Type: Application
    Filed: April 12, 2024
    Publication date: October 3, 2024
    Inventors: Dmitri A. Yudanov, Shanky Kumar Jain
  • Patent number: 12101260
    Abstract: When a measure of buffer space queued for garbage collection in a network device grows beyond a certain threshold, one or more actions are taken to decreasing an enqueue rate of certain classes of traffic, such as of multicast traffic, whose reception may have caused and/or be likely to exacerbate garbage-collection-related performance issues. When the amount of buffer space queued for garbage collection shrinks to an acceptable level, these one or more actions may be reversed. In an embodiment, to more optimally handle multi-destination traffic, queue admission control logic for high-priority multi-destination data units, such as mirrored traffic, may be performed for each destination of the data units prior to linking the data units to a replication queue. If a high-priority multi-destination data unit is admitted to any queue, the high-priority multi-destination data unit can no longer be dropped, and is linked to a replication queue for replication.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: September 24, 2024
    Assignee: Innovium, Inc.
    Inventors: William Brad Matthews, Puneet Agarwal, Bruce Hui Kwan, Ajit Kumar Jain
  • Publication number: 20240314583
    Abstract: Embodiments herein provide a method for prioritizing disoriented cells in a wireless network by an electronic device. The method includes determining a morphology factor of each disoriented cell of a plurality of disoriented cells. Further, the method includes determining a cell type of each disoriented cell of the plurality of disoriented cells based on the morphology factor of each disoriented cell of the plurality of disoriented cells. Further, the method includes determining a PRB utilization of each disoriented cell of the plurality of disoriented cells. Further, the method includes determining a number of RRC connected users of each disoriented cell of the plurality of disoriented cells. Further, the method includes determining a priority for each disoriented cell of the plurality of disoriented cells based on the morphology factor, the cell type, the PRB utilization, and the RRC connected users.
    Type: Application
    Filed: December 28, 2022
    Publication date: September 19, 2024
    Applicant: RAKUTEN SYMPHONY INDIA PRIVATE LIMITED
    Inventors: Durgesh RATHORE, Atul RAJPOOT, Sudeep Kumar JAIN, Nilesh BANKAR
  • Publication number: 20240314424
    Abstract: A device and method are provided for providing a function related to a camera in an electronic device. A method includes acquiring, via a first camera of the electronic device, a plurality of first images; acquiring, via a second camera of the electronic device, one or more second images; generating a plurality of image contents based on at least one of the plurality of first images or the one or more second images; and outputting the plurality of image contents at respective regions of a display of the electronic device.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Inventors: Sunho MOON, Yeonjong Bong, Ramakrishnan Srinivasakannan, Gaurav Kumar Jain, Girish Kulkarni, Karthikeyan Somanathan, Sachin Dev, Sudha Velusamy, Uison Yoon, Jehan Yoon, Cheolyong Jeon, Kihuk Lee
  • Patent number: 12093243
    Abstract: Systems and techniques for metadata quality monitoring and remediation are described herein. Metadata is obtained from a system of record. The metadata is normalized. The metadata is evaluated with an integrity rule to identify a discrepancy in an element of the metadata. The discrepancy is stored as an integrity gap in an integrity database. A notification is generated that includes identification of the element of the metadata and a description of the integrity rule. The notification is transmitted to a user identified based on the integrity rule.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: September 17, 2024
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Rajiv Kumar Jain, Christopher James McBrayer
  • Patent number: 12092965
    Abstract: A defect prediction method for a device manufacturing process involving processing one or more patterns onto a substrate, the method including: determining values of one or more processing parameters under which the one or more patterns are processed; and determining or predicting, using the values of the one or more processing parameters, an existence, a probability of existence, a characteristic, and/or a combination selected from the foregoing, of a defect resulting from production of the one or more patterns with the device manufacturing process.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: September 17, 2024
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Venugopal Vellanki, Vivek Kumar Jain, Stefan Hunsche
  • Publication number: 20240298155
    Abstract: Various arrangements for configuring wireless network access for a first wireless device using a previously-configured second wireless device are presented. The first wireless device may output a temporary wireless network hotspot and advertise an identifier. A second wireless device may search for and identify the first wireless device based on the advertised identifier. The second wireless device may connect with the temporary wireless network hotspot and provide wireless network credentials for a wireless network for which the second wireless device has previously been granted access. The first wireless device may then establish a network connection with the wireless network based on the wireless network credentials transmitted by the second wireless device.
    Type: Application
    Filed: October 27, 2023
    Publication date: September 5, 2024
    Inventor: Vikal Kumar Jain
  • Patent number: 12079484
    Abstract: A method includes receiving a value and an identifier from a first memory and hashing the identifier to produce a memory block identifier. The method also includes routing, based on the memory block identifier, a read request to a memory block of a plurality of memory blocks and updating the value received from the first memory based on a property received from the memory block in response to the read request. The memory further includes storing the updated value in the first memory.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: September 3, 2024
    Assignee: XILINX, INC.
    Inventors: Abhishek Kumar Jain, Henri Fraisse, Dinesh D. Gaitonde
  • Patent number: 12081218
    Abstract: A multiphase digital frequency synthesizer including a multiphase ring oscillator that provides phased clock signals, a clock divider that divides a phased clock signal by an integer value and a carry value to provide a divided clock signal, positive select circuitry that determines and updates a positive select value with accumulation and a modulo function based on a fractional division factor updated with successive cycles of the divided clock signal, carry circuitry that determines the carry value based on a number of the phased clock signals, positive multiplex circuitry that selects from among the phased clock signal using the positive select value for providing a positive multiplexed clock signal, and fractional phase addition circuitry that provides a first output clock signal based on a selected phased clock signal, the divided clock signal, and the positive multiplexed clock signal. Similar negative select circuitry and duty cycle correction circuitry may be included.
    Type: Grant
    Filed: April 6, 2023
    Date of Patent: September 3, 2024
    Assignee: NXP USA, Inc.
    Inventors: Ravi Kumar, Gaurav Agrawal, Deependra Kumar Jain, Krishna Thakur
  • Publication number: 20240289380
    Abstract: Methods, computer systems, computer-storage media, and graphical user interfaces are provided for determining user affinities by tracking historical user interactions with tagged digital content and using the user affinities in content generation applications. Accordingly, the system may track user interactions with published digital content in order to generate user interaction reports whenever a user engages with the digital content. The system may aggregate the interaction reports to generate an affinity profile for a user or audience of users. A marketer may then generate digital content for a target user or audience of users and the system may process the digital content to generate a set of tags for the digital content. Based on the set of tags, the system may then evaluate the digital content in view of the affinity profile for the target user/audience to determine similarities or differences between the digital content and the affinity profile.
    Type: Application
    Filed: May 6, 2024
    Publication date: August 29, 2024
    Inventors: Yaman Kumar, Vinh Ngoc Khuc, Vijay Srivastava, Umang Moorarka, Sukriti Verma, Simra Shahid, Shirsh Bansal, Shankar Venkitachalam, Sean Steimer, Sandipan Karmakar, Nimish Srivastav, Nikaash Puri, Mihir Naware, Kunal Kumar Jain, Kumar Mrityunjay Singh, Hyman Chung, Horea Bacila, Florin Silviu Lordache, Deepak Pai, Balaji Krishnamurthy
  • Publication number: 20240292445
    Abstract: Some embodiments of the invention provide a system for mitigating inter-region interference for multiple regions serviced by multiple RAN (Radio Access Network) base stations. The system includes a first RAN application for generating a map that identifies, for each particular region serviced by each particular RAN base station, a set of one or more sub-regions receiving interfering signals from other RAN base stations. The system includes a second RAN application for (1) using the generated map and a set of input received from the plurality of RAN base stations to define, for each sub-region in the set of sub-regions, policies for allocating carrier resources of the particular RAN base station to carrier beams transmitted by the particular RAN base station to the sub-regions with the interfering signals, and (2) providing the defined policies to the RAN base stations for which the policies are defined.
    Type: Application
    Filed: July 12, 2023
    Publication date: August 29, 2024
    Inventors: Yang Yang, Neha Paranjape, Deepa Muthunoori, Ish Kumar Jain
  • Publication number: 20240291624
    Abstract: Some embodiments of the invention provide a method for mitigating inter-region interference for multiple regions serviced by multiple RAN (Radio Access Network) base stations. The method is performed for each region serviced by each particular RAN base station. The method identifies a set of one or more sub-regions receiving interfering signals from other RAN base stations.
    Type: Application
    Filed: July 12, 2023
    Publication date: August 29, 2024
    Inventors: Yang Yang, Neha Paranjape, Deepa Muthunoori, Ish Kumar Jain
  • Publication number: 20240292390
    Abstract: Some embodiments of the invention provide a method for operating a first base station of a radio access network (RAN). At the first base station, the method receives a set of allow and block policies for allocating carrier resources to carrier beams utilized by the first base station for mobile devices within a first region serviced by the first base station, said first region located near a second region serviced by a second base station. At the first base station, the method identifies a first mobile device operating in the first region. At the first base station, the method uses the set of allow and block policies to allocate carrier resources to a carrier beam used to communicate with the first mobile device in the first region.
    Type: Application
    Filed: July 12, 2023
    Publication date: August 29, 2024
    Inventors: Yang Yang, Neha Paranjape, Deepa Muthunoori, Ish Kumar Jain
  • Patent number: 12073877
    Abstract: Systems and methods are provided for limiting a negative bit line voltage in a SRAM cell. A voltage limiter circuit may be implemented in a write driver to control the magnitude of negative voltage imposed on a bit line. The voltage limiter circuit can produce the required magnitude of negative bit line voltage at lower operating voltage levels. The voltage limiter circuit can also limit the magnitude of negative bit line voltage to not exceed a predetermined value. The reduction of the magnitude of the negative bit line voltage can reduce the active power of a SRAM cell.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: August 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sanjeev Kumar Jain, Atul Katoch
  • Publication number: 20240281171
    Abstract: Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable read broadcast operations. A read broadcast may occur from the memory array to multiple locations of the signal development cache, for example via one or more multiplexers.
    Type: Application
    Filed: February 27, 2024
    Publication date: August 22, 2024
    Inventors: Dmitri A. Yudanov, Shanky Kumar Jain
  • Patent number: 12064137
    Abstract: A medical device includes an elongated body (14) and a plurality of sensors (10) conformally formed on the elongated body at a plurality of longitudinal positions along the elongated body. The plurality of sensors is configured to generate signals in accordance with detected energy for an imaging system. A single electrical trace (24) connects to each of the plurality of sensors, the plurality of sensors being connected in parallel to form an array of sensors along the elongated body.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: August 20, 2024
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Ramon Quido Erkamp, Ameet Kumar Jain, Francois Guy Gerard Marie Vignon