Abstract: Structures for a silicon-controlled rectifier and methods of forming same. The structure comprises a first well, a second well, and a third well in a semiconductor substrate. The third well is positioned between the first well and the second well. A first terminal includes a first doped region in the first well, and a second terminal includes a second doped region in the second well. The first well, the second well, and the second doped region have a first conductivity type, and the third well and the first doped region have a second conductivity type opposite to the first conductivity type. The structure further comprises a third doped region in the third well. The third doped region includes a first segment and a second segment, and the first segment is separated from the second segment by a portion of the first well and a portion of the third well.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

Abstract: Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable read broadcast operations. A read broadcast may occur from the memory array to multiple locations of the signal development cache, for example via one or more multiplexers.

Abstract: A cell range determination is made by determining a sector straddling an azimuth line of a first base station with a center at the coordinates of a first base station. The sector is divided into a plurality of subsectors. A nearest neighbor base station is determined in each of the plurality of subsectors. A set of coordinates is determined for the nearest neighbor base station. An average distance between the nearest neighbor base stations is determined. A bearing angle difference between the nearest neighbor base station and the first base station is determined based on the set of coordinates of the nearest neighbor base station. A gain is determined for each of the plurality of subsectors based on the bearing angle difference. A cell range is determined for the first base station based on the gain.

Abstract: A multiphase digital frequency synthesizer including a multiphase ring oscillator that provides phased clock signals, a clock divider that divides a phased clock signal by an integer value and a carry value to provide a divided clock signal, positive select circuitry that determines and updates a positive select value with accumulation and a modulo function based on a fractional division factor updated with successive cycles of the divided clock signal, carry circuitry that determines the carry value based on a number of the phased clock signals, positive multiplex circuitry that selects from among the phased clock signal using the positive select value for providing a positive multiplexed clock signal, and fractional phase addition circuitry that provides a first output clock signal based on a selected phased clock signal, the divided clock signal, and the positive multiplexed clock signal. Similar negative select circuitry and duty cycle correction circuitry may be included.

Abstract: Disclosed herein are related to reducing power consumption of a memory device when transitioning from a sleep state to an operational state. In one aspect, the memory device includes a memory cell to store data. In one aspect, the memory device includes an output driver configured to: generate an output signal indicating the stored data, in response to a sleep tracking signal indicating that the memory cell is in the operational state, and generate the output signal having a predetermined voltage irrespective of the stored data, in response to the sleep tracking signal indicating that the memory cell is in the sleep state. In one aspect, the sleep tracking signal is delayed from a sleep control signal causing the memory cell to operate in the sleep state or the operational state.

Abstract: Provided is a method for generating Augmented Reality (AR) content that includes: receiving a plurality of image frames of at least one scene captured by a plurality of participant devices in an AR or a Virtual Reality (VR) environment; storing the plurality of image frames and metadata associated with the plurality of image frames, in a database; receiving an AR content generation request to generate an AR content view of a user in the AR/VR environment, the AR content generation request including an identifier (ID) of the user and information of the at least one scene; retrieving a set of image frames from a plurality of stored image frames in the database based on the ID of the user, the information of the at least one scene, and metadata associated with the set of image frames, the set of images including the user in the at least one scene in the AR/VR environment; generating the AR content view of the user by combining the set of image frames retrieved from the database, based on the metadata associated

Abstract: A memory circuit includes a global control circuit, a first local control circuit, and a first set of word line post-decoder circuits coupled to a first set of memory cells that is configured to store a first set of data. The global control circuit is configured to generate a first and second set of global pre-decoder signals, and a first set of local address signals. The first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. The first set of repeater circuits is configured to generate a first and second set of local pre-decoder signals in response to the corresponding first and second set of global pre-decoder signals. The first clock pre-decoder circuit is configured to generate a first and second set of clock signals in response to the first set of local address signals and the first clock signal.

Abstract: Systems and method are provided for operating a multi-array memory that includes a left memory array and a right memory array of a memory bank. A command is received at memory input pins. A signal representative of the command is propagated to an array control inhibitor. An array inhibit command is received on one or more other pins of the memory and provided to the array control inhibitor. The array control inhibitor is used to prevent arrival of the command to one of the left memory array and the right memory array based on the array inhibit command.

Abstract: A Phase Locked Loop (PLL) with reduced jitter includes: a phase detector, for comparing the phases of a reference clock and feedback clock to generate up and down control signals; a Voltage Controlled Oscillator (VCO) for generating an oscillation signal; an output divider, for dividing the oscillation signal to generate an output clock; a fractional feedback divider for receiving the oscillation signal and performing frequency division on the oscillation signal according to a modulated sequence to generate a modulated clock; and a divider coupled in series to the fractional feedback divider, for dividing the modulated clock of the fractional feedback divider by a fixed modulus to generate a divided clock. A frequency of the modulated clock of the fractional feedback divider is an integer multiple of the frequency of the divided clock, and one of the modulated clock and divided clock is used as the feedback clock.

Abstract: In one embodiment, a device sends data traffic to a gateway of a backhaul mesh network via a first wireless access point of the backhaul mesh network. The device maintains, while associated with the first wireless access point, an association with a second wireless access point of the backhaul mesh network by sending a frame to the first wireless access point that is relayed by the first wireless access point to the second wireless access point. The device makes a determination that additional data traffic should be sent to the gateway of the backhaul mesh network via the second wireless access point. The device sends, based on the determination, the additional data traffic to the gateway of the backhaul mesh network via the second wireless access point.

Abstract: Systems and methods are provided for a memory device. A memory device includes a memory array, a column selection circuit coupled to the memory array, where the column selection circuit is configured to generate a column selection signal, and a sense amplifier configured to receive data signals from the memory array. An enable signal generating circuit is configured to generate a first enable signal and a second enable signal. The column selection circuit generates the column selection signal based on the first enable signal, and the sense amplifier is configured to receive a data signal from the memory array in response to the second enable signal.

Abstract: Systems and methods are provided for controlling a sleep operation for a memory array. A memory system may include a memory array with a memory cell and a word line driver, the memory array receiving a word line clock signal that enables and disables memory read and write operations of the memory cell. The memory array may further including a switching circuit coupled between the word line driver and a power source, the switching circuit being controlled by a local word line sleep signal to turn power to the word line driver on and off. A latch circuit may generate the local word line sleep signal in response to a delayed clock signal and one or more power management control signals. The word line clock signal and the delayed clock signal may both being generated as a function of a memory clock signal.

Abstract: Disclosed herein is a time-based leaderboard that ranks users based on a length of time each user has controlled or possessed a given digital object. The leaderboard includes customization options for purposes of user identification and identity connected to social network objects. The leaderboard further uses a staking feature where users provide their digital objects to universal wallets to hold for a predetermined period based on smart contract limitations. Staking improves leaderboard position. The leaderboard further enables expression and displayed of staked digital objects despite the user no longer having actual possession of the digital object. A digital object generator builds unique digital objects based on the user specific input. The unique digital objects are part of a graphic presentation to users.

Abstract: Techniques are provided that rotate a device address used to identify a wireless client device on a wireless network. The wireless client device and at least one network infrastructure component identify a plurality of device addresses associated with the wireless client device. In some embodiments, the plurality of device addresses are generated via a corresponding plurality of invocations of a stateful random number generator, such as a cryptographically secure pseudorandom number generator.

Abstract: A data processing system is configured to perform a computer implemented method for facilitation of efficient processing of electronic messages via a network from message sources. The method includes receiving an electronic message including actionable object data and textual object data from a message source device. The actionable object data includes parameters actionable by at least one data processing transaction device to perform data processing transactions external to the network device and the textual object data including descriptors of the parameters actionable by the at least one data processing transaction device. The textual object data is operable by devices incompatible with the actionable object data. The method includes calculating an execution command for the data processing transaction in response to the actionable object data and based on at least the parameters of the actionable object data.

Abstract: Content creation techniques are described that leverage content analytics to provide insight and guidance as part of content creation. To do so, content features are extracted by a content analytics system from a plurality of content and used by the content analytics system as a basis to generate a content dataset. Event data is also collected by the content analytics system from an event data source. Event data describes user interaction with respective items of content, including subsequent activities in both online and physical environments. The event data is then used to generate an event dataset. An analytics user interface is then generated by the content analytics system using the content dataset and the event dataset and is usable to guide subsequent content creation and editing.

Abstract: A Phase Locked Loop (PLL) with reduced jitter includes: a phase detector, for comparing the phases of a reference clock and feedback clock to generate up and down control signals; a Voltage Controlled Oscillator (VCO) for generating an oscillation signal; an output divider, for dividing the oscillation signal to generate an output clock; a fractional feedback divider for receiving the oscillation signal and performing frequency division on the oscillation signal according to a modulated sequence to generate a modulated clock; and a divider coupled in series to the fractional feedback divider, for dividing the modulated clock of the fractional feedback divider by a fixed modulus to generate a divided clock. A frequency of the modulated clock of the fractional feedback divider is an integer multiple of the frequency of the divided clock, and one of the modulated clock and divided clock is used as the feedback clock.

Abstract: An example method of upgrading a distributed storage object from a first version to a second version includes: querying metadata of a first component configured according to the first version of the distributed storage object, the metadata defining extents of data on a disk group of the first component; populating, for a second component configured according to the second version of the distributed storage object, logical and middle maps based on the metadata such that initial entries in the logical map point to initial entries in the middle map, and the initial entries in the middle map point to physical addresses of the disk group of the first component; and reading the data from the disk group of the first component and writing the data to a disk group of the second component while updating the initial entries in the middle map.

Abstract: Systems and methods are provided for learning classifiers for annotating a document with predicted labels under extreme classification where there are over a million labels. The learning includes receiving a joint graph including documents and labels as nodes. Multi-dimensional vector representations of a document (i.e., document representations) are generated based on graph convolution of the joint graph. Each document representation varies an extent of reliance on neighboring nodes to accommodate context. The document representations are feature-transformed using a residual layer. Per-label document representations are generated from the transformed document representations based on neighboring label attention. A classifier is trained for each of over a million labels based on joint learning using training data and the per-label document representation. The trained classifier performs highly efficiently as compared to other classifiers trained using disjoint graphs of documents and labels.