Patents by Inventor Kumar Srivastava

Kumar Srivastava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10817454
    Abstract: An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: October 27, 2020
    Assignee: Intel Corporation
    Inventors: Chih-Cheh Chen, Janusz P. Jurski, Amit Kumar Srivastava, Malay Trivedi, James Mitchell, Piotr Michael Kwidzinski, David N. Lombard
  • Publication number: 20200336508
    Abstract: Disclosed is a method and a system for using techniques to stitch cybersecurity, generate network risks and predictive mitigations. The method includes collecting data from several data sources and labeling events. The method includes creating a profile for each entity observed in the data with the behavior of the profile determined through the analytical analysis of the events in which the entity participates including the transference of labels from events to the entity. One or more profiles of an organization are identified that have changed and the change is processed using specific attack sequence detection to identify one or more risks associated with each profile. The method further includes notifying one or more users associated with the one or more profiles based on the one or more risks.
    Type: Application
    Filed: July 4, 2020
    Publication date: October 22, 2020
    Inventor: Kumar Srivastava
  • Patent number: 10811546
    Abstract: A process of depositing zirconium oxide (ZrO2) layers possessing dual properties of anti-reflection and passivation of silicon surfaces, including passivation of n-type and p-type silicon substrates. To grow a ZrO2 anti-reflection passivation layer, a precursor layer of zirconium oxide is spun on a silicon surface then dried, pyrolyzed and fired at suitable contact firing conditions, avoiding additional deposition. Thermal annealing in a hydrogen environment improves passivation quality of ZrO2 layer to a level 3-4 times higher than that of fired films alone. ZrO2 dielectric passivation layers exhibit improved passivation quality after illumination due to photo-enhanced passivation and higher passivation quality at higher thermal budget suitable for screen printed metal contact firing, unlike standard PECVD deposited passivation layers. The method is adaptable for fabrication of silicon solar cells and other structures utilizing passivated layers.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: October 20, 2020
    Assignee: Council of Scientific & Industrial Research
    Inventors: Prathap Pathi, Rani Kalpana, Vandana, Sanjay Kumar Srivastava, Chandra Mohan Singh Rauthan, Parakram Kumar Singh
  • Patent number: 10803219
    Abstract: A method for a combined formal static analysis of a design code, the method comprising using a lint checker performing Lint checks to identify a suspected violation in the design code; using a formal static analyzer, performing formal checks to identify a suspected property that corresponds to the suspected violation; applying a formal proof technique to determine whether the suspected property is proven or disproved; and if the suspected property is disproved, issuing an alert.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: October 13, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Maayan Ziv, Hanna Nizar, Kanwar Pal Singh, Sudeep Kumar Srivastava
  • Publication number: 20200322475
    Abstract: According to an embodiment, there is provided an electronic device comprising: a memory storing instructions; and at least one processor configured to execute the instructions to: generate state information regarding a device state of the electronic device of a first user and communication information regarding communications of the first user with a second user; transmitting the state information and the communication information to a server or an electronic device of the second user, wherein the state information and the communication information are used to determine communication availability of the first user and to provide the second user with information regarding the communication availability of the first user.
    Type: Application
    Filed: December 4, 2018
    Publication date: October 8, 2020
    Inventors: Sunil RATHOUR, Nitesh GOYAL, Pratush Kumar SRIVASTAVA, Ankit AGARWAL, Ekta Anil Pardeep SACHDEV, Ridhima JAISWAL, Reetika MITTAL, Vobbilisetty SUSHANT, Desh Deepak AGARWAL, Anuj MAHAJAN, Aasheesh NAIN
  • Patent number: 10790731
    Abstract: A method of forming a coating on a component of an electrical machine is presented. The method includes coating a surface of the component with a ceramic material, via an electrophoretic process, to form a first coating. The method further includes contacting the first coating deposited by the electrophoretic process with a polymeric material to form a second coating. The method furthermore includes curing or melting the polymeric material in the second coating to form the coating including the ceramic material dispersed in a polymer matrix.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 29, 2020
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Weijun Yin, Anil Raj Duggal, Aharon Yakimov, Holly Ann Comanzo, Vijay Kumar Srivastava, Mohandas Nayak, Hao Huang, Oltea Puica Siclovan, Paul Michael Smigelski, Jr.
  • Patent number: 10769084
    Abstract: Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (I2C) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an I2C device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the I2C OBI, an I3C IBI that includes information related to the I2C OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Kenneth P. Foust, Duane G. Quiet, Amit Kumar Srivastava
  • Patent number: 10745023
    Abstract: A voltage monitoring framework is proposed to predict, report, and correct actions for performance impacting voltage droop due to power supplies in a system-on-a-chip. Both the amplitude and duration of the voltage droop are monitored. By predicting serious voltage droops early, power supplies cross check against each other to avoid catastrophic error, thus ensuring that integrated circuits making up the system-on-a-chip will maintain functional reliability.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 18, 2020
    Assignee: INTEL CORPORATION
    Inventors: Amit Kumar Srivastava, Asad Azam, Jagannadha Rapeta
  • Publication number: 20200257601
    Abstract: Techniques and mechanisms for exchanging debug information with a repeater and multiplex logic of a platform. In an embodiment, the multiplex logic can be configured to any of multiple modes including a first mode to exchange debug information between the repeater and debug client logic of the platform. Another of the multiple modes may provide an alternate communication path for exchanging functional data, other than any debug information, between the repeater and a physical layer interface of the platform. In another embodiment, the repeater is compatible with a repeater architecture identified by a universal serial bus standard. The physical layer interface is compatible with an interface specification identified by the same universal bus standard.
    Type: Application
    Filed: October 13, 2016
    Publication date: August 13, 2020
    Inventors: Amit Kumar SRIVASTAVA, Huimin CHEN
  • Patent number: 10739836
    Abstract: In one embodiment, an apparatus includes: at least one processing circuit; at least one array associated with the at least one processing circuit; a power controller to manage power consumption of the apparatus; and a fabric bridge coupled to the power controller. The fabric bridge and power controller may be configured to implement a handshaking protocol to enable the fabric bridge to receive data from the at least one array via a sideband communication path and send the data to a system memory coupled to the apparatus via a primary communication path, prior to entry of the apparatus into a first low power state. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Robert Milstrey, Amit Kumar Srivastava
  • Publication number: 20200249276
    Abstract: Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for in-field safety tests on system-level and circuit-level, providing real-time and on-chip tests with respect to, including but not limited to, circuit reliability, power consumption, and system safety. The in-field safety tests may include implementing voltage droop monitors (VDMs) and signature collectors with authentication-enabled launching. Other embodiments may be described and claimed.
    Type: Application
    Filed: February 1, 2019
    Publication date: August 6, 2020
    Inventors: Lakshminarayana Pappu, Amit Kumar Srivastava, Robert Milstrey
  • Patent number: 10733626
    Abstract: A system and method for real-time generation of segments for a computerized decision system provides an event segment list to a decision engine. The event segment list is generated based on consumer affinities determined from consumer data and modeled data on that consumer's consumption and geo-location. The consumer affinities are used in a query to obtain current events related to the consumer's affinities. The current events are associated with generic events, which together are included in the event segment list, which is delivered to the decision engine and used to make a decision based on the event segment list and specified decision criteria.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: August 4, 2020
    Assignee: DISNEY ENTERPRISES, INC.
    Inventors: Vikram Somaya, Ajit Kumar Srivastava, Molly Parr, Sophie M. Coleman, Christen Johnson Chattleton, Scott T. Keating
  • Publication number: 20200242516
    Abstract: An AI platform to enable one or more users to design and create AI enabled applications is provided. The AI platform comprises a data module configured to condition data received from a plurality of data sources to generate a corresponding data pipeline; wherein the data module comprises a plurality of reusable data components. The AI platform further comprises an intelligent processing module configured to process a plurality of datasets received on the data pipeline and generate a corresponding artificial intelligence (AI) pipeline; wherein the intelligent processing module comprises a plurality of reusuable data processing components.
    Type: Application
    Filed: May 14, 2019
    Publication date: July 30, 2020
    Inventors: Deepinder Singh Dhingra, Ganesh Moorthy, Praveen Singh, Sarfaraj Ahmad, Arijit Saha, Kumar Srivastava, Sourabh Chourasia, Ted Gaubert
  • Publication number: 20200244269
    Abstract: An apparatus is provided which comprises: a first ring oscillator comprising at least one aging tolerant circuitry; a second ring oscillator comprising a non-aging tolerant circuitry; a first counter coupled to the first ring oscillator, wherein the first counter is to count a frequency of the first ring oscillator; a second counter coupled to the second ring oscillator, wherein the second counter is to count a frequency of the second ring oscillator; and logic to compare the frequencies of the first and second ring oscillators, and to generate one or more controls to mitigate aging of one or more devices.
    Type: Application
    Filed: February 3, 2020
    Publication date: July 30, 2020
    Applicant: Intel Corporation
    Inventor: Amit Kumar Srivastava
  • Patent number: 10705594
    Abstract: A Universal Serial Bus 2.0 (USB2 or eUSB2) device includes an integrated circuit (IC) having a physical layer to send and receive data on a pair of signal lines, a repeater communicatively coupled to the physical layer via the pair of signal lines, and having a port to send and receive data on a second pair of signal lines and a power management unit to provide power to the physical layer and the repeater during an active state and to gate power to the physical layer and the repeater during a low power state.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: July 7, 2020
    Assignee: INTEL CORPROATION
    Inventor: Amit Kumar Srivastava
  • Publication number: 20200213232
    Abstract: An ingress fabric endpoint coupled to a switch fabric within a network device reorders packet flows based on congestion status. In one example, the ingress fabric endpoint receives packet flows for switching across the switch fabric. The ingress fabric endpoint assigns each packet for each packet flow to a fast path or a slow path for packet switching. The ingress fabric endpoint processes, to generate a stream of cells for switching across the switch fabric, packets from the fast path and the slow path to maintain a first-in-first-out ordering of the packets within each packet flow. The ingress fabric endpoint switches a packet of a first packet flow after switching a packet of a second packet flow despite receiving the packet of the first packet flow before the packet of the second packet flow.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Anuj Kumar Srivastava, Gary Goldman, Harshad B. Agashe, Dinesh Jaiswal, Piyush Jain, Naveen K. Jain
  • Patent number: 10692363
    Abstract: This disclosure relates to method and system for determining probability of an alarm generated by an alarm system. The method may include receiving sensor data and maintenance data. The sensor data may include one or more environmental parameters and one or more trigger parameters, and the alarm is generated based on the one or more trigger parameters. The method may further include generating one or more input vectors based on the sensor data and the maintenance data, and determining a spuriosity index of the alarm based on the one or more input vectors using a machine learning model. The machine learning model may be created using historical sensor data and historical maintenance data, and the spuriosity index is indicative of the probability of the alarm.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: June 23, 2020
    Assignee: Wipro Limited
    Inventors: Anurag Kumar Srivastava, Utkarsh Bhakne
  • Publication number: 20200175847
    Abstract: This disclosure relates to method and system for determining probability of an alarm generated by an alarm system. The method may include receiving sensor data and maintenance data. The sensor data may include one or more environmental parameters and one or more trigger parameters, and the alarm is generated based on the one or more trigger parameters. The method may further include generating one or more input vectors based on the sensor data and the maintenance data, and determining a spuriosity index of the alarm based on the one or more input vectors using a machine learning model. The machine learning model may be created using historical sensor data and historical maintenance data, and the spuriosity index is indicative of the probability of the alarm.
    Type: Application
    Filed: January 29, 2019
    Publication date: June 4, 2020
    Inventors: Anurag Kumar Srivastava, Utkarsh Bhakne
  • Patent number: 10664027
    Abstract: The disclosed embodiments relate to methods, systems and apparatus for dynamic temperature aware functional safety. The disclosed embodiments provide adaptive techniques to track extended dynamic temperature range of a System-on-Chip (SOC) and automatically tune critical IP components of the SOC so that system can operate reliably even at high temperatures. The disclosed embodiments relax the overdesign of the SOC components by reusing existing components such as a ring oscillator to determine temperature at different regions of the SOC. In one embodiment, the disclosed principles use a Calibrated Ring Oscillator (CRO) temperature sensors. The CRO-based temperature sensors provide fast temperature measurement suitable for detecting dynamic temperature ranges and temperature rate of change. The CROs are existing on the SOC and do not require addition of additional sensors.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Amit Kumar Srivastava, Rao Jagannadha Rapeta, Asad Azam
  • Patent number: 10657152
    Abstract: Methods and systems for generating a diagram from structured data and synchronizing modifications between the diagram and the structured data. One system includes at least one processor configured to receive a plurality of transformation settings for the structured data and generate and store a plurality of first expressions and a plurality of second expressions based on the structured data and the plurality of transformation settings. The processor is further configured to generate and organize a plurality of visual structures based on the plurality of first expressions and the plurality of second expressions and generate and output a diagram for display through a user interface including the plurality of visual structures. In addition, the processor is configured to receive a modification to the diagram through the user interface, and modify the structured data based on the modification, the plurality of first expressions, and the plurality of second expressions.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: May 19, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mukundan Bhoovaraghavan, Sandeep Kumar Srivastava, Amit Joshi, Salony Jain, Manjeet Bothra, Shashank Gandhi, Ashutosh Tripathi