Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a gate structure disposed on the substrate. The semiconductor device also includes a source region and a drain region disposed within the substrate. The substrate includes a drift region laterally extending between the source region and the drain region. The semiconductor device further includes a first stressor layer disposed over the drift region of the substrate. The first stressor layer is configured to apply a first stress to the drift region of the substrate. In addition, the semiconductor device includes a second stressor layer disposed on the first stressor layer. The second stressor layer is configured to apply a second stress to the drift region of the substrate, and the first stress is opposite to the second stress.

Abstract: A power delivery device and a control method are shown. The power delivery device includes a power factor correction circuit, and an output voltage control circuit. The power factor correction circuit is configured to increase a power factor of the power delivery device. The output voltage control circuit is configured to control an output voltage of the power delivery device, and detect an output current of the power delivery device. The power factor correction circuit is uncontrolled by the output voltage control circuit in response to a first load state of the power delivery device, and is controlled by the output voltage control circuit in response to a second load state of the power delivery device.

Abstract: A power delivery device and a control method are shown. The power delivery device includes a power factor correction circuit, and an output voltage control circuit. The power factor correction circuit is configured to increase a power factor of the power delivery device. The output voltage control circuit is configured to control an output voltage of the power delivery device, and detect an output current of the power delivery device. The power factor correction circuit is uncontrolled by the output voltage control circuit in response to a first load state of the power delivery device, and is controlled by the output voltage control circuit in response to a second load state of the power delivery device.

Abstract: A power delivery device and a control method are shown. The power delivery device includes a power conversion circuit, a power factor correction circuit, and an output voltage control circuit. The power conversion circuit includes a primary side and a secondary side, and is configured to receive an input voltage and convert the input voltage to an output voltage. The power factor correction circuit is electrically coupled to the primary side and configured to increase the power factor of the power delivery device. The output voltage control circuit is electrically coupled to the secondary side and configured to control the voltage level of the output voltage. When the voltage level of the output voltage is lower than a predetermined level, the power factor correction circuit is deactivated.

Abstract: A power delivery device and a control method are shown. The power delivery device includes a power conversion circuit, a power factor correction circuit, and an output voltage control circuit. The power conversion circuit includes a primary side and a secondary side, and is configured to receive an input voltage and convert the input voltage to an output voltage. The power factor correction circuit is electrically coupled to the primary side and configured to increase the power factor of the power delivery device. The output voltage control circuit is electrically coupled to the secondary side and configured to control the voltage level of the output voltage. When the voltage level of the output voltage is lower than a predetermined level, the power factor correction circuit is deactivated.

Abstract: A wall socket includes a socket housing, an output terminal, a power converter circuit and a load detection circuit. The output terminal is arranged at a side of the socket housing and configured to output a DC output voltage. The power converter circuit is arranged in the socket housing and configured to convert an input voltage to the DC output voltage according to a control signal. The load detection circuit is configured to receive an identification signal outputted by an electronic device when the electronic device is connected to the output terminal, and output the control signal according to the identification signal to adjust a voltage level of the DC output voltage.

Abstract: A wall socket is disclosed herein. The wall socket includes a socket housing, an output terminal, a power converter circuit and a load detection circuit. The output terminal is arranged at a side of the socket housing and configured to output a DC output voltage. The power converter circuit is arranged in the socket housing and configured to convert an input voltage to the DC output voltage according to a control signal. The load detection circuit is configured to receive an identification signal outputted by an electronic device when the electronic device is connected to the output terminal, and output the control signal according to the identification signal to adjust a voltage level of the DC output voltage.

Abstract: A power supply apparatus with input voltage detection includes a power input side and an input detection module. The power input side has a first input terminal and a second input terminal, and the first input terminal and the second input terminal are electrically connected to a live wire and a neutral wire of an AC power source, respectively. The input detection module has two input terminals, which are corresponding electrically connected to the first input terminal and the second input terminal. The input detection module generates a detection signal to shut down the power supply apparatus when the input detection module detects that the live wire or the neutral wire is abnormal, or the live wire and the neutral wire are both abnormal.

Abstract: A power supply apparatus with input voltage detection includes a power input side and an input detection module. The power input side has a first input terminal and a second input terminal, and the first input terminal and the second input terminal are electrically connected to a live wire and a neutral wire of an AC power source, respectively. The input detection module has two input terminals, which are corresponding electrically connected to the first input terminal and the second input terminal. The input detection module generates a detection signal to shut down the power supply apparatus when the input detection module detects that the live wire or the neutral wire is abnormal, or the live wire and the neutral wire are both abnormal.

Abstract: An output voltage detecting circuit includes a conducting structure, a voltage regulator, a first resistor and a second resistor. The conducting structure includes a power output return terminal, a first contact and a second contact. A compensating voltage is generated between the first and second contacts when an output current flows through the first and second contacts. The voltage regulator adjusts a first current according to a voltage across a first circuit terminal and the ground terminal of the voltage regulator, thereby generating a detecting signal according to the first current. An output voltage across the positive power output terminal and the power output return terminal is subject to voltage division by the first and second resistors to generate a divided voltage. The voltage across the first circuit terminal and the ground terminal of the voltage regulator is equal to a difference between the divided voltage and the compensating voltage.

Abstract: An output voltage detecting circuit includes a conducting structure, a voltage regulator, a first resistor and a second resistor. The conducting structure includes a power output return terminal, a first contact and a second contact. A compensating voltage is generated between the first and second contacts when an output current flows through the first and second contacts. The voltage regulator adjusts a first current according to a voltage across a first circuit terminal and the ground terminal of the voltage regulator, thereby generating a detecting signal according to the first current. An output voltage across the positive power output terminal and the power output return terminal is subject to voltage division by the first and second resistors to generate a divided voltage. The voltage across the first circuit terminal and the ground terminal of the voltage regulator is equal to a difference between the divided voltage and the compensating voltage.

Abstract: A power supply device and an operating method thereof are provided. The power supply device includes a main converter and an auxiliary converter. The main converter includes a power factor corrector (PFC), a first capacitor that connects in parallel with the PFC and a DC/DC converter that connects in parallel with the first capacitor. The auxiliary converter is connected in parallel to the main converter. When the power supply device operates in a normal mode, the main converter and the auxiliary converter together provide a first output to an output load. When the power supply device is in a standby mode, the DC/DC converter is turned off so that only the auxiliary converter provides a second output to the output load. Meanwhile, the PFC is in operation to maintain the voltage of the first capacitor in order to meet the demand of the output dynamic response of the main converter.

Abstract: A power supply device and an operating method thereof are provided. The power supply device includes a main converter and an auxiliary converter. The main converter comprises a power factor corrector (PFC), a first capacitor that connects in parallel with the PFC and a DC/DC converter that connects in parallel with the first capacitor. The auxiliary converter is connected in parallel to the main converter. When the power supply device operates in a normal mode, the main converter and the auxiliary converter together provide a first output to an output load. When the power supply device is in a standby mode, the DC/DC converter is turned off so that only the auxiliary converter provides a second output to the output load. Meanwhile, the PFC is in operation to maintain the voltage of the first capacitor in order to meet the demand of the output dynamic response of the main converter.

Abstract: A method of fabricating a node contact on a substrate, which contains a first conductive device and an insulating layer covering the substrate and the first conductive device, includes forming at least two conductive lines on the insulating layer, wherein the conductive lines are separated by a first distance; forming at least two second conductive devices on the insulating layer, wherein the second conductive devices are separated by a second distance, and wherein one of the conductive lines and one of the second conductive devices are separated by a third distance, and wherein both the first and second distances are greater than the third distance; forming an isolation layer of a thickness on the substrate to cover the insulating layer, the conductive lines and the second conductive devices, wherein the isolation layer comprises a dished area located between the second conductive devices; removing a portion of the isolation layer to form a spacer around the second conductive devices, and to deepen the dishe

Abstract: A multi-chip package which has a L-shaped plate and a plurality of dies arranged on the L-shaped plate. The L-shaped plate has a die package region, a plurality of solder bump pads disposed in the die package region, a plurality of pins electrically connected to a printed circuit board (PCB), and an internal circuit inside the L-shaped plate electrically connected to the plurality of solder bump pads and corresponding pins. Each die includes a plurality of bonding pads on an active surface of the die, and the bonding pads are electrically connected to corresponding solder bump pads.

Abstract: The present invention explains a method for manufacturing a MOS transistor of an embedded memory. The method of present invention is to first define a memory array area and a periphery circuit region on the surface of the semiconductor wafer followed by forming each gate, a spacer of each gate, and lightly doped drain (LDD) in memory array area. A stop layer and a dielectric layer are formed on the surface of semiconductor. Then, the dielectric layer in periphery circuit regions is removed followed by forming each gate in the periphery circuit regions. Lightly doped drain (LDD) adjacent each gate and on sidewalls of gate, a spacer, a source, and a drain are formed in periphery circuit regions. Finally, a self-aligned silicide (salicide) process is performed for forming a silicide layer on the surface of each gate, source and drain.

Abstract: The present invention provides a method for landing pads in the semiconductor devices, comprising the following steps: providing a semiconductor substrates with a plurality of active regions, a plurality of gate structures above the active regions and a plurality of source/drain regions, while each gate structure comprises a top cap layer and sidewall spacers; forming a conductive layer over the substrate; removing a portion of the conductive layer above the gate structure using the top cap layer of the gate structure as a stop layer, so that a height of the conductive layer is lower than a height of the gate structure; forming a patterned mask layer, right above the active regions, over the substrate; performing an etching step to define the conductive layer above the active regions; and removing the patterned mask layer and forming landing pads on the active regions.

Abstract: A fabrication method for an ultra-small opening is described, wherein a first photoresist layer is formed on a substrate. Exposure and development processes are further conducted to transfer the desired pattern with a small opening from the mask layer onto the surface of the first photoresist layer. A plasma treatment is then conducted on the first photoresist layer, followed by coating a second photoresist layer on the first photoresist layer.

Abstract: A method of fabricating a node contact on a substrate, which contains a first conductive device and an insulating layer covering the substrate and the first conductive device, includes forming at least two conductive lines on the insulating layer, wherein the conductive lines are separated by a first distance; forming at least two second conductive devices on the insulating layer, wherein the second conductive devices are separated by a second distance, and wherein one of the conductive lines and one of the second conductive devices are separated by a third distance, and wherein both the first and second distances are greater than the third distance; forming an isolation layer of a thickness on the substrate to cover the insulating layer, the conductive lines and the second conductive devices, wherein the isolation layer comprises a dished area located between the second conductive devices; removing a portion of the isolation layer to form a spacer around the second conductive devices, and to deepen the dishe

Abstract: The present invention provides a method for landing pads in the semiconductor devices, comprising the following steps: providing a semiconductor substrates with a plurality of active regions, a plurality of gate structures above the active regions and a plurality of source/drain regions, while each gate structure comprises a top cap layer and sidewall spacers; forming a conductive layer over the substrate; removing a portion of the conductive layer above the gate structure using the top cap layer of the gate structure as a stop layer, so that a height of the conductive layer is lower than a height of the gate structure; forming a patterned mask layer, right above the active regions, over the substrate; performing an etching step to define the conductive layer above the active regions; and removing the patterned mask layer and forming landing pads on the active regions.