Patents by Inventor Kun-Chi Lin
Kun-Chi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6162678Abstract: A method for fabricating a type of bit line is able to form a small-sized bit line. In this method a first dielectric layer, a first conductive layer, and a second conductive layer are formed on a substrate in sequence. The first dielectric layer is exposed, then a second conducting wire and a first conducting wire are formed, respectively. A portion of the second conducting wire is removed by a cleaning liquid, so that the feature size of the second conducting wire is less than the feature size of the first conducting wire. An oxide layer is formed on the second conducting wire and the first conducting wire by performing a thermal treatment. The feature size of the second conducting wire is approximately equal to the feature size of the first conducting wire.Type: GrantFiled: November 9, 1998Date of Patent: December 19, 2000Assignee: United Microelectronics Corp.Inventors: Kevin Lin, Ching-Chiao Hao, Kun-Chi Lin
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Patent number: 6159806Abstract: A method for depositing an oxide layer after spacer formation is disclosed. Owing to an oxide layer after spacer formation, therefore substantially increasing the effective thickness of spacer of the peripheral circuit. The method includes which includes a substrate on which an interior and a peripheral circuit are defined, wherein there is a gate oxide layer formed on the substrate. Sequentially an interior gate and a peripheral gate are formed. Then, N-type ions are implanted into the substrate of the interior and peripheral circuit. Consequently, conformal a second dielectric layer and a third dielectric layer are deposited above the substrate, interior gate, and peripheral gate, wherein second dielectric layer is etched to form a spacer of the interior gate and the peripheral gate. And then N.sup.+ -type ions are implanted into the substrate to form source/drain by using the peripheral gate, the spacer and a portion of the third dielectric layer that runs along the spacer as a mask.Type: GrantFiled: December 29, 1999Date of Patent: December 12, 2000Assignee: United Microelectronics Corp.Inventors: Horng-Nan Chern, Hsi-Chia Lin, Kun-Chi Lin
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Patent number: 6150216Abstract: A method for forming an electrode of semiconductor device capacitor is disclosed. The method comprises forming a dielectric layer on a semiconductor substrate and then using photolithographic method to etch a trench through the dielectric layer to expose specific part of the semiconductor substrate. A polysilicon layer is then formed over the dielectric layer and filled the trench. The polysilicon layer is patterned by a photoresist layer and etched back to the dielectric layer, then a polysilicon rod is formed. A spacer method is used to form an amorphized silicon spacer is sidewall of the polysilicon rod. The polysilicon rod is then implanted to form an amorphized polysilicon layer on top surface of the polysilicon rod. Final hemispherical grain silicon is formed on the spacer and the amorphized polysilicon layer to increase the surface area of the polysilicon rod. Thereby, an electrode of a semiconductor device capacitor is formed, and the capacitance of capacitor is enhanced.Type: GrantFiled: December 29, 1998Date of Patent: November 21, 2000Assignee: United Microelectronics Corp.Inventors: Kuo-Chi Lin, Kun-Chi Lin
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Patent number: 6150223Abstract: A method for forming a different width of gate spacer is disclosed. The method includes firstly forming a gate oxide layer on a semiconductor substrate. A polysilicon layer, a conductive layer, a first dielectric layer are formed in order on the gate oxide layer. The first dielectric layer, the conductive layer, the polysilicon layer, and the gate oxide layer are further etched using them as the interior gate and the peripheral gate. Next, second dielectric layer, third dielectric layer, and fourth dielectric layer are formed over the interior gate and the peripheral gate, and a first photoresist layer abuts the surface of the fourth dielectric layer of the interior circuit. Moreover, etching the fourth dielectric layer of peripheral gate to form a second spacer of peripheral gate, and etching the third dielectric layer of the peripheral gate are undertaken to form a first spacer of the peripheral gate.Type: GrantFiled: April 7, 1999Date of Patent: November 21, 2000Assignee: United Microelectronics Corp.Inventors: Horng-Non Chern, Kun-Chi Lin, Alex Hou, Chien-Hua Tsai, Tsu-An Lin
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Patent number: 6150278Abstract: An improved method of fabricating a node capacitor for a dynamic random access memory (DRAM) process is disclosed. The process includes depositing a first interpoly dielectric (IPD1) layer over a substrate, patterning a first photoresist layer on the first interpoly dielectric layer, thereby defining a trench. A trench is etched in the first interpoly dielectric layer using the first photoresist layer as a mask. A first polysilicon layer is deposited on the first interpoly dielectric layer. The first polysilicon layer is etched to expose the first interpoly dielectric layer, then forming a landing pad over the substrate. In order to a polycide layer and a second interpoly dielectric (IPD2) layer are deposited, patterning a second photoresist layer, thereby defining a bit line structure. A bit line structure is formed, then depositing a spacer on the bit line structure. A second polysilicon layer is deposited, patterning a third photoresist layer, thereby defining a bottom electrode.Type: GrantFiled: July 20, 1999Date of Patent: November 21, 2000Assignee: United Microelectronics Corp.Inventors: Wayne Tan, Kun-Chi Lin
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Patent number: 6150263Abstract: A method of forming small dimension wires by an isotropic removal process. The method provides a substrate with an insulation layer. A first conductive layer and a second conductive layer are formed on the insulation layer. A wire pattern is formed on a photoresist layer after the coating process and the sequential exposure and development process. Part of the second conductive layer is removed by using the wire pattern on the photoresist layer as a mask, and thus part of the second conductive layer with wires is remained. Isotropic etching the peripheral part of the second conductive layer and thus the part of wire pattern with a smaller dimension is remained. Using the wire pattern with a smaller dimension as a mask to anisotropic etch the first conductive layer until the surface of the insulation layer is exposed, and thus the process of fabricating small dimension is finished.Type: GrantFiled: November 9, 1998Date of Patent: November 21, 2000Assignee: United Microelectronics Corp.Inventors: Kevin Lin, Ching-Chiao Hao, Kun-Chi Lin
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Patent number: 6140202Abstract: A method for fabricating a double-cylinder capacitor is provided. The double-cylinder capacitor has a storage electrode having dual, concentric cylinder structures. The dielectric layer and the top electrode are formed in sequence over the bottom electrode. The storage area is thus enlarged by the double-cylinder capacitor of the invention. Thus, the capacitance of the capacitor can be effectively increased.Type: GrantFiled: December 8, 1998Date of Patent: October 31, 2000Assignee: United Microelectronics Corp.Inventors: Horng-Nan Chern, Kun-Chi Lin
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Patent number: 6140168Abstract: A method of fabricating a self-aligned contact window includes forming an undoped dielectric layer on a substrate having a least gate structure. The dopants are implanted into a pre-determined region of the undoped dielectric layer and the dielectric layer with the dopants is then removed. A self-aligned contact is therefore completed.Type: GrantFiled: February 1, 1999Date of Patent: October 31, 2000Assignee: United Microelectronics Corp.Inventors: Wayne Tan, Kun-Chi Lin
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Patent number: 6136642Abstract: A method of fabricating a dynamic random access memory includes forming a dummy layer over the isolation layer, in which the dummy layer has a higher etching selectivity than oxide. A dielectric layer is applied to isolate the bit lines. Then, a passivation layer is formed over the entire structure and a node contact opening is formed thereon. A liner oxide layer is then formed in the node contact opening to isolate the bit lines and the electrode of the capacitor. The node contact opening has a larger misalignment tolerance.Type: GrantFiled: December 23, 1998Date of Patent: October 24, 2000Assignee: United Microelectronics Corp.Inventors: Wayne Tan, Kun-Chi Lin
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Patent number: 6124161Abstract: A method for forming a hemispherical silicon grain (HSG) layer on a polysilicon electrode is provided. The method is suitable for a substrate, which has a dielectric layer over the substrate with an opening to expose the substrate, and a polysilicon layer is formed over the substrate. A portion of the polysilicon layer is removed above dielectric layer other than the opening region. Each sidewall of the polysilicon layer is slanted so that a trapezoidal polysilicon base is formed. A buffer layer is formed over the trapezoidal polysilicon base. An ion implantation process is performed to form an amorphous silicon layer with sufficient depth on a top surface region of the trapezoidal polysilicon base. The buffer layer includes silicon oxide or silicon nitride. During ion implantation, oxygen or nitrogen elements can also be bombarded into the amorphous silicon layer so as to buffer the amorphous silicon layer to be re-crystallized. A selective HSG layer is formed on the trapezoidal polysilicon electrode base.Type: GrantFiled: December 1, 1998Date of Patent: September 26, 2000Assignee: United Microelectronics Corp.Inventors: Horng-Nan Chern, Kevin Lin, Kun-Chi Lin
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Patent number: 6100014Abstract: A semiconductor fabrication method is provided for forming an opening in a dielectric layer, which can help downsize the critical dimension of the resulting opening through the use of a photoresist layer with silylated sidewall spacers. By this method, the first step is to coat a base photoresist layer over the dielectric layer. Next, a photolithographic process is performed to remove a selected part of the base photoresist layer. Then, a conformational coating process is performed to coat a silylatable photoresist layer over the base photoresist layer to a controlled predefined thickness. Subsequently, a silylation process is performed on the silylatable photoresist layer so as to form a silylated photoresist layer over all the exposed surfaces of the base photoresist layer. After this, a first etching process is performed on the silylated photoresist layer, with the remaining portions of the silylated photoresist layer serving as silylated sidewall spacers on the base photoresist layer.Type: GrantFiled: November 24, 1998Date of Patent: August 8, 2000Assignee: United Microelectronics Corp.Inventors: Benjamin Szu-Min Lin, Kun-Chi Lin
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Patent number: 6100158Abstract: A method of manufacturing an alignment mark. A substrate having a device region and an alignment mark region is provided. The device region is higher than the alignment mark region. The device region comprises an active region. An isolation structure is formed in the substrate at the edge of the alignment mark region and a first dielectric layer is formed over a portion of the substrate at the alignment mark region, simultaneously. A conductive layer is formed over the substrate. A portion of the conductive layer is removed to expose the first dielectric layer at the alignment mark region. The remaining conductive layer is patterned to form a component at the active region. A second dielectric layer with a smooth surface is formed over the substrate to cover the component. A wire is formed on the second dielectric layer, wherein a distance between the wire and the alignment mark region is larger than a distance between the component and the alignment mark region.Type: GrantFiled: April 30, 1999Date of Patent: August 8, 2000Assignee: United Microelectronics Corp.Inventors: Tzung-Han Lee, Kun-Chi Lin, Horng-Nan Chern, Alex Hou
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Patent number: 6096594Abstract: The present invention provides a fabricating method and structure of a dynamic random access memory. In this method, a substrate having a transistor thereon is provided. A bit line is formed on the substrate. The bit line is electrically coupled with the transistor through a contact hole. A second dielectric layer having a node contact opening is formed on the bit line. An etching step is performed to etch the bit line. A concave surface is formed on the sidewall of the bit line. Spacer layers are formed on the sidewalls of the node contact opening. Each spacer layer is used to insulate the concave surface. Thus, from the top-view layout, a portion of the node contact opening can overlap with the bit line. Thus, the size of DRAM is effectively reduced.Type: GrantFiled: November 9, 1998Date of Patent: August 1, 2000Assignee: United Microelectronics Corp.Inventors: Kun-Chi Lin, Chia-Wen Liang, Hal Lee
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Patent number: 6074955Abstract: A method of fabricating a node contact window. A substrate having devices and a first dielectric layer is provided. Bit lines having spacer are formed on the first dielectric layer and a second is formed on the first dielectric layer. A hard material layer is then formed on the second dielectric layer. An opening is formed within the second dielectric layer to expose the spacer and the first dielectric layer. A polysilicon spacer is then formed on the sidewalls of the opening. A node contact window is formed by etching through the first dielectric layer to expose the substrate.Type: GrantFiled: November 9, 1998Date of Patent: June 13, 2000Assignee: United Microelectronics Corp.Inventors: Kevin Lin, Chia-Wen Liang, Kun-Chi Lin
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Patent number: 5861333Abstract: The present invention includes forming a first field oxide region (FOX) on a substrate. Buried N.sup.+ regions are then formed. Subsequently, a plurality of second FOX regions are formed. A tunneling window region between the second FOX regions is narrowed by the formation of the second FOX regions. Then a tunnel oxide is formed on the substrate. A first polysilicon layer is deposited on the first FOX, the second FOXs, the gate oxide, the tunnel oxide and the substrate. An etching step is used to define the floating gate. A dielectric layer is formed on the floating gate. A second polysilicon layer is then formed on the dielectric layer. The second polysilicon layer and the dielectric layer are etched. An ion implantation step is used to form source and drain of the gate.Type: GrantFiled: October 25, 1996Date of Patent: January 19, 1999Assignee: United Microelectonics Corp.Inventor: Kun-Chi Lin