Patents by Inventor Kun Fang

Kun Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220149421
    Abstract: Disclosed is a battery cell, a battery, an electric apparatus, and a manufacturing method of the battery, belonging to the technical field of batteries. The battery includes an electrode assembly, an electrode terminal and a current collector, the current collector is configured to connect the electrode assembly and the electrode terminal; where the current collector and the electrode terminal are connected through a welding portion; and the welding portion is exposed at an external peripheral surface of the current collector and/or an external peripheral surface of the electrode terminal. The battery cell, the battery, the electric apparatus, and the manufacturing method of the battery are capable of ensuring the safety of the battery.
    Type: Application
    Filed: December 16, 2021
    Publication date: May 12, 2022
    Applicant: JIANGSU CONTEMPORARY AMPEREX TECHNOLOGY LIMITED
    Inventor: Kun FANG
  • Publication number: 20220115312
    Abstract: A substrate that includes a core layer, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, a plurality of first interconnects located over a surface of the at least one first dielectric layer, a plurality of second interconnects located over the surface of the at least one first dielectric layer, a plurality of third interconnects located over the surface of the at least one first dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. The plurality of third interconnects and the plurality of second interconnects are co-planar to the plurality of first interconnects. The solder resist layer includes a first portion, a second portion, and a third portion.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 14, 2022
    Inventors: Kun FANG, Jaehyun YEON, Suhyung HWANG, Hong Bok WE
  • Publication number: 20220082468
    Abstract: A system for detecting leakage of a liquid supply pipe includes a pipe casing for enclosing an end portion of the liquid supply pipe adjoined to a nozzle and a sensor system configured to detect presence of a liquid leaked from the liquid supply pipe at the end portion. The sensor system is in alignment with the end portion of the liquid supply pipe.
    Type: Application
    Filed: November 23, 2021
    Publication date: March 17, 2022
    Inventors: Yu Kai CHEN, Li-Jen WU, Chin-Kun FANG, Ko-Bin KAO
  • Patent number: 11273396
    Abstract: A system for dispensing a liquid includes a filter adapted to filter a liquid and to provide a filtered liquid at a liquid outlet of the filter, and a tank having a liquid inlet coupled to the liquid outlet of the filter via a first pipe. The tank includes an upper portion having a first lateral dimension and a lower portion having a second lateral dimension less than the first lateral dimension. The upper portion of the tank is above the liquid inlet of the tank.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: March 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Y. L. Huang, Chin-Kun Fang, Li-Jen Wu, Yu Kai Chen
  • Publication number: 20220068662
    Abstract: A substrate that includes a core layer comprising a first surface and a second surface, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, high-density interconnects located over a surface of the at least one second dielectric layer, interconnects located over the surface of the at least one second dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. A first portion of the solder resist layer that is touching the high-density interconnects includes a first thickness that is equal or less than a thickness of the high-density interconnects. A second portion of the solder resist layer that is touching the interconnects includes a second thickness that is greater than a thickness of the interconnects.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 3, 2022
    Inventors: Kun FANG, Jaehyun YEON, Suhyung HWANG, Hong Bok WE
  • Publication number: 20220053639
    Abstract: A package that includes a substrate and an electrical component coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, and a solder resist layer located over a surface of the at least one dielectric layer. The solder resist layer includes a first solder resist layer portion comprising a first thickness, and a second solder resist layer portion comprising a second thickness that is less than the first thickness. The electrical component is located over the second solder resist layer portion.
    Type: Application
    Filed: January 14, 2021
    Publication date: February 17, 2022
    Inventors: Kun FANG, Jaehyun YEON, Suhyung HWANG, Hyunchul CHO, Boyu TSENG
  • Patent number: 11199466
    Abstract: A system for detecting leakage of a liquid supply pipe includes a pipe casing for enclosing an end portion of the liquid supply pipe adjoined to a nozzle and a sensor system configured to detect presence of a liquid leaked from the liquid supply pipe at the end portion. The sensor system is in alignment with the end portion of the liquid supply pipe.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu Kai Chen, Chin-Kun Fang, Ko-Bin Kao, Li-Jen Wu
  • Patent number: 11183446
    Abstract: X.5 layer substrates that do not use an embedded traces substrate process during formation may produce a high yield with relaxed L/S in a short manufacturing time (only 4× lamination process without a detach process) at a low cost. For example, a substrate may include an mSAP, two landing pads, two escape lines, two bump pads, and a photo-imageable dielectric layer on the mSAP patterned substrate.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: November 23, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Jaehyun Yeon, Suhyung Hwang, Hong Bok We, Kun Fang
  • Publication number: 20210255963
    Abstract: “A system in having M memory controllers between a first memory and a second memory having N operative memory slices, where N and M are not evenly divisible, includes logic to operate the M memory controllers to linearly distribute addresses of the second memory across the N operative memory slices. The system may be utilized in commercial applications such as data centers, autonomous vehicles, and machine learning.
    Type: Application
    Filed: April 13, 2021
    Publication date: August 19, 2021
    Applicant: NVIDIA Corp.
    Inventors: Prakash Bangalore Prabhakar, James M. Van Dyke, Kun Fang
  • Patent number: 11022695
    Abstract: A GBAS integrity risk allocation system based on key satellites is used to perform a GBAS integrity risk allocation method, including: reading data from an ephemeris at a certain time, and determining numbers of key satellites, key satellite pairs and key satellite groups at a certain time; under H2 hypothesis, allocating the integrity risks by using the fault probability of satellites in key satellite pairs or key satellite groups, where the integrity risks allocated by using the fault probability of satellites in key satellite pairs or key satellite groups include integrity risks caused by dual-receiver fault and integrity risks caused by ranging source fault; under H0 and H1 hypotheses, allocating the integrity risks by using the fault probability of non-key satellites; making an integrity allocation table according to the integrity risk allocation under the H0, H1 and H2 hypotheses.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: June 1, 2021
    Assignee: BEIHANG UNIVERSITY
    Inventors: Kun Fang, Yanbo Zhu, Zhen Gao, Zhipeng Wang
  • Patent number: 10983919
    Abstract: An addressing scheme in systems utilizing a number of operative memory slices in a last level cache that is not evenly divisible by a number of memory channels utilizes the operative slices exposes the full last level cache bandwidth and capacity to data processing logic in a high-performance graphics system.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: April 20, 2021
    Assignee: NVIDIA Corp.
    Inventors: Prakash Bangalore Prabhakar, James M Van Dyke, Kun Fang
  • Patent number: 10969497
    Abstract: A dynamic baseline position domain monitoring system based on satellite navigation and inertial navigation is used to perform a method, including: a) determining a coordinate system and a transformation matrix; b) calculating a theoretical coordinate value of an antenna baseline vector in a earth-centered earth-fixed coordinate system during the movement of a base station carrier; c) determining the number of antenna baseline vectors to be monitored; d) solving the measurement values of the antenna baseline vectors; e) calculating the position domain error of an antenna baseline vector change rate in three directions of x, y and z at epoch k, and normalizing the position domain errors to obtain a normalized value of the position domain errors; f) obtaining the a cumulative sum; g) comparing the cumulative sum with an error monitoring threshold value, and issuing an integrity risk alarm.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: April 6, 2021
    Assignee: BEIHANG UNIVERSITY
    Inventors: Zhipeng Wang, Yanbo Zhu, Kai Kang, Kun Fang, Qiang Li
  • Publication number: 20210089465
    Abstract: An addressing scheme in systems utilizing a number of operative memory slices in a last level cache that is not evenly divisible by a number of memory channels utilizes the operative slices exposes the full last level cache bandwidth and capacity to data processing logic in a high-performance graphics system.
    Type: Application
    Filed: September 25, 2019
    Publication date: March 25, 2021
    Applicant: NVIDIA Corp.
    Inventors: Prakash Bangalore Prabhakar, James M. Van Dyke, Kun Fang
  • Publication number: 20210049097
    Abstract: Techniques are disclosed for allocating a global memory space defined within physical memory devices into strided memory space(s) (SMS) and partition memory space(s) (PMS). In an embodiment, a SMS is mapped across all of the devices, and a PMS is mapped to a subset of the devices to ensure resource isolation between separate PMSs. Typically, a memory space is allocated in unit sizes. When the locations mapped to most of the SMS align to an integer number of the unit size, a common boundary can be formed between the SMS and the one or more PMSs in each of the devices. Such a boundary can advantageously minimize a region of locations that are not available for allocation in the global memory spaces. In an embodiment, when a strided allocation is not an integer number of the unit size, a remainder is mapped to locations for one or more PMSs.
    Type: Application
    Filed: August 15, 2019
    Publication date: February 18, 2021
    Inventors: Kun Fang, James M. Van Dyke
  • Patent number: 10909033
    Abstract: Techniques are disclosed for allocating a global memory space defined within physical memory devices into strided memory space(s) (SMS) and partition memory space(s) (PMS). In an embodiment, a SMS is mapped across all of the devices, and a PMS is mapped to a subset of the devices to ensure resource isolation between separate PMSs. Typically, a memory space is allocated in unit sizes. When the locations mapped to most of the SMS align to an integer number of the unit size, a common boundary can be formed between the SMS and the one or more PMSs in each of the devices. Such a boundary can advantageously minimize a region of locations that are not available for allocation in the global memory spaces. In an embodiment, when a strided allocation is not an integer number of the unit size, a remainder is mapped to locations for one or more PMSs.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: February 2, 2021
    Assignee: NVIDIA Corporation
    Inventors: Kun Fang, James M. Van Dyke
  • Patent number: 10852439
    Abstract: The present invention provides a global ionospheric total electron content prediction system based on a spatio-temporal sequence hybrid framework. The prediction system implements computational processing for two types of spatio-temporal sequences, wherein for a stationary spatio-temporal sequence, a STARMA model prediction method is constructed in the present invention; for a non-stationary spatio-temporal sequence, a nonlinear spatio-temporal trend is firstly extracted from the non-stationary spatio-temporal sequence by adopting a ConvLSTM method until the extracted residual passes a stationarity test, and then the electron content is predicted using the STARMA model prediction method.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: December 1, 2020
    Assignee: BEIHANG UNIVERSITY
    Inventors: Zhipeng Wang, Cheng Wang, Kaiyu Xue, Kun Fang
  • Patent number: 10782418
    Abstract: The present invention provides a calculation method for visual navigation integrity monitoring. With the method, by use of an appropriate visual positioning model, a mathematical algorithm and rich navigation measurements, the positioning accuracy and availability of positioning results are improved, and the problem of insufficient performance of satellite integrity algorithms caused by impossible guarantee of availability of a GNSS in complex environments is solved, which is helpful to realize aircraft accurate approach and automatic landing and of great significance to ensure the safety of aviation flight.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: September 22, 2020
    Assignee: BEIHANG UNIVERSITY
    Inventors: Zhipeng Wang, Yanbo Zhu, Cong Du, Kun Fang, Qiang Li
  • Patent number: 10768312
    Abstract: The present invention provides an integrity analysis method based on a kinematic-to-kinematic relative positioning scenario, including the following steps: a) establishing a kinematic-to-kinematic relative positioning model, and inputting navigation data; b) calculating a float solution of an integer ambiguity; c) detecting and correcting cycle slips based on a total electron content rate; d) calculating a probability of correct fix and a probability of incorrect fix for the integer ambiguity; e) determining a fault to be detected and a satellite fault probability; 0 calculating a standard deviation ?_(v|CF) and a position domain deviation b_m; and g) calculating an integrity risk value of a carrier phase. The present invention provides an integer ambiguity calculation algorithm for a kinematic-to-kinematic positioning system in the case of a long baseline, to calculate carrier phase integrity.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: September 8, 2020
    Assignee: BEIHANG UNIVERSITY
    Inventors: Zhipeng Wang, Yanbo Zhu, Xiaopeng Hou, Kun Fang
  • Patent number: 10732289
    Abstract: The present invention provides a LDACS-based air-ground cooperative positioning method. According to the method, on the basis of LDACS, users are classified into super-high-altitude users, high-altitude users, and low-altitude users, and air-ground cooperative positioning is implemented through information exchange among the users at the three levels. Meanwhile, a new fault mode and an integrity hazard are introduced into the method. Therefore, the present invention further provides a method for monitoring the integrity of a LDACS-based air-ground cooperative positioning method, including a fault detection algorithm and a protection level solving method; and proposes a method for evaluating the complexity of integrity monitoring. The LDACS-based air-ground cooperative positioning method provided in the present invention well solves the problem of the shortage of APNT services in poor terrain conditions, making the positioning results more accurate.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: August 4, 2020
    Assignee: BEIHANG UNIVERSITY
    Inventors: Zhipeng Wang, Yanbo Zhu, Xin Li, Kun Fang, Jingtian Du
  • Patent number: 10612378
    Abstract: A method for recovering room-mining coal pillars by solid filling in synergy with artificial pillars. Solid materials and cementing materials on the ground are conveyed through a feeding well and a pipeline to a room-and-pillar goaf, a plurality of artificial pillars is cast at an interval in a coal room area, and gangue is cast to fill other regions of the coal room using a gangue casting machine. Under joint support by the artificial pillars and the coal room filler, coal pillars are recovered using a continuous coal mining machine, artificial pillars are cast in the original coal pillar area after recovery, and gangue is cast to fill the original coal pillar area using the gangue casting machine. A system for recovering room-mining coal pillars by solid filling in synergy with artificial pillars mainly includes a material conveying system, a joint support system, and a coal pillar recovery system.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: April 7, 2020
    Assignee: CHINA UNIVERSITY OF MINING AND TECHNOLOGY
    Inventors: Jixiong Zhang, Qiang Zhang, Xiancheng Mei, Kun Fang, Xiaole Han