Abstract: A method for fabricating a memory device is provided: A multi-layer stack is formed on a substrate. The multi-layer stack is then patterned to form plural trenches extending along a first direction to define plural ridge-shaped stacks each of which comprises at least one conductive strip. Next, a memory layer and a channel layer are formed in sequence on bottoms and sidewalls of the trenches. A sacrifice layer is formed to fulfill the trenches. Subsequently, portions of the sacrifice layer, the memory layer and the channel layer formed in the trenches are removed to form plural openings exposing a portion of the substrate therefrom. After removing the remaining sacrifice layer, portions of the memory layer and the channel layer formed on the ridge-shaped stacks are patterned to form an interconnection between two adjacent trenches through two of the openings formed in the two adjacent trenches.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate having a trench, a stacked strip structure formed in the trench, and at least a conductive structure. The stacked strip structure includes a plurality of interlaced conductive strips and insulating strips. Each of the conductive strips has a horizontal conductive segment and two vertical conductive segments connected to the corresponding horizontal conductive segment. Each of the insulating strips has a horizontal insulating segment and two vertical insulating segments. The conductive structure is electrically connected to at least one of the conductive strips. The stacked strip structure has a horizontal stacked portion corresponding to the horizontal conductive segments and two vertical stacked portions corresponding to the vertical conductive segments, wherein a width of the vertical stacked portions is larger than a thickness of the horizontal stacked portion.

Abstract: A 3D stacked semiconductor structure is provided, comprising a plurality of multi-layered pillars formed on a substrate and spaced apart from each other, a plurality of first conductors formed between the adjacent multi-layered pillars, a plurality of charging-trapping layers formed on the substrate and on the sidewalls of the multi-layered pillars for separating the first conductor and the multi-layered pillars, and a second conductor formed on the first conductors and on the charging-trapping layers. One of the multi-layered pillars comprises a plurality of insulating layers and a plurality of conductive layers arranged alternately. The top surfaces of the first conductors are higher than the top surfaces of the multi-layered pillars so as to create a plurality of receiving trenches respectively on the multi-layered pillars. The second conductor fills up the receiving trenches on the multi-layered pillars.

Abstract: A memory device includes a first metal layer and a second metal layer, a metal oxide layer disposed between the first metal layer and the second metal layer, and at least one oxygen control layer disposed between the metal oxide layer and at least one of the first metal layer and the second metal layer. The at least one oxygen control layer has a graded oxygen content.

Abstract: A method for manufacturing a printed circuit board is disclosed, which comprises the following steps. A basic board having an upper surface and a bottom surface opposite to the upper surface is provided. A plurality of the electronic components temporarily disposed on the basic board is provided. At least one locating pin temporarily disposed on a place of the basic board is provided, in which the electronic components are not temporarily disposed on the place. Surface mount technology is used simultaneously to joint at least one locating pin and the electronic components on the basic board.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a stacked structure, a dielectric layer, a conductive structure, a dielectric structure and a conductive plug. The stacked structure includes dielectric films and conductive films arranged alternately. The dielectric layer is between the conductive structure and a sidewall of the stacked structure. The dielectric structure is on the stacked structure and defining a through via. The conductive plug fills the through via and physically contacts one of the conductive films exposed by the through via and adjoined with the dielectric layer.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a stack of alternate conductive layers and insulating layers, an opening, an oxide layer and a conductor. The stack is formed on the substrate. The opening penetrates through the stack. The oxide layer is formed on a sidewall of the opening. The conductor is filled into the opening. The conductor is separated from the sidewall of the opening by only the oxide layer.

Abstract: A self-rectified device is provided, comprising a bottom electrode, a patterned dielectric layer with a contact hole formed on the bottom electrode, a memory formed at the bottom electrode and substantially aligned with the contact hole, and a top electrode formed on the bottom electrode and filling into the contact hole to contact with the memory, wherein the top electrode comprises a N+ type semiconductor material or a P+ type semiconductor material, and the memory and the top electrode produce a self-rectified property.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a conductive layer, a conductive architecture and a dielectric layer. The conductive layer defines adjacent first openings. The conductive architecture surrounds a portion of the conductive layer between the first openings. The dielectric layer separates the conductive layer and the conductive architecture.

Abstract: Metal oxide based memory devices and methods for manufacturing are described herein. A method for manufacturing a memory cell includes forming an insulation layer on an access device followed by forming vias through the insulation layer to expose the first and second access device terminals. First and second interlayer conductors extending through the vias are formed next. Top surfaces of the interlayer conductors are oxidized to form oxide layers. The oxide layer on the first interlayer conductor forms a memory layer. On top of the insulation layer a layer of protection metal is formed covering the oxide layers. The layer of protection metal is patterned and etched to form a top electrode layer covering the memory layer. The oxide layer on the second interlayer conductor is removed. Parallel first and second access lines are then formed on the top electrode layer and the second interlayer conductor, respectively.

Abstract: A semiconductor structure and a manufacturing method of the same are disclosed. The semiconductor structure includes a conductive layer, a conductive strip, a dielectric layer, and a conductive element. The conductive layer has a first conductive material. The conductive strip is in the same level as the conductive layer and has a second conductive material. The second conductive material is adjoined with the first conductive material having a conductivity characteristic different from a conductivity characteristic of the second conductive material. The conductive element crisscrosses the conductive strip and separated from the conductive strip by the dielectric layer.

Abstract: A display device includes a first substrate, at least one trace, a hydrophobic protective layer, a flexible printed circuit board (FPCB), a second substrate and a sealant. The first substrate has a display region and a peripheral region having an outer lead bonding (OLB) portion. The trace and the hydrophobic protective layer are disposed on the first substrate and extend from the display region to the OLB portion. The hydrophobic protective layer covers the trace and has at least one opening exposing a portion of the trace to define at least one lead and a surface microstructure. The lead and the surface microstructure are located in the OLB portion, and the surface microstructure is located on a surface of the hydrophobic protective layer away from the trace. One end of the FPCB leans against the surface microstructure and the FPCB is electrically connected to the lead.

Abstract: A memory device includes a first metal layer and a second metal layer, a metal oxide layer disposed between the first metal layer and the second metal layer, and at least one oxygen control layer disposed between the metal oxide layer and at least one of the first metal layer and the second metal layer. The at least one oxygen control layer has a graded oxygen content.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method comprises the following steps. First, a stack of alternate sacrificial layers and insulating layers is formed on a bottom layer on a substrate. Then, a plurality of first holes and a plurality of second holes are formed through the stack concurrently. In the semiconductor structure as formed by the embodied method, the first holes and the second holes are equally spaced apart from each other at least in an arranged direction.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a conductive layer, a conductive architecture and a dielectric layer. The conductive layer defines adjacent first openings. The conductive architecture surrounds a portion of the conductive layer between the first openings. The dielectric layer separates the conductive layer and the conductive architecture.

Abstract: A method of manufacturing a three-dimensional (3D) stacked semiconductor structure is provided, comprising. A multi-layer on a substrate is formed, and the multi-layer comprises plural first dielectric layers and second dielectric layers arranged alternately. The multi-layer is then patterned to form plural first patterned stacks and spaces between the first patterned stacks, wherein one of the first patterned stacks has a width of F0 while the one of the spaces has a width of Fs. In one embodiment, F0 is equal to or more than 2 times Fs. Parts of the second dielectric layers of one of the first patterned stacks are removed, so as to form plural first cavities in the first patterned stack. Then, the first cavities in the first patterned stack are filled with conductors.

Abstract: A method of manufacturing a three-dimensional (3D) stacked semiconductor structure is provided, comprising. A multi-layer on a substrate is formed, and the multi-layer comprises plural first dielectric layers and second dielectric layers arranged alternately. The multi-layer is then patterned to form plural first patterned stacks and spaces between the first patterned stacks, wherein one of the first patterned stacks has a width of FO while the one of the spaces has a width of Fs. In one embodiment, FO is equal to or more than 2 times Fs. Parts of the second dielectric layers of one of the first patterned stacks are removed, so as to form plural first cavities in the first patterned stack. Then, the first cavities in the first patterned stack are filled with conductors.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a stacked strip structure, and a tensile material strip. The stacked strip structure is formed vertically on the substrate, the stacked strip structure having compressive stress. The stacked strip structure comprises a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. The tensile material strip is formed on the stacked strip structure, the tensile material strip having tensile stress.

Abstract: A semiconductor structure and a manufacturing method for the same are provided. The method includes following steps. A first gate structure is formed on a substrate in a first region. A protecting layer is formed covering the first gate structure. A second gate structure is formed on the substrate in second region exposed by the protecting layer and adjacent to the first region.

Abstract: A memory device includes an array of strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. A plurality of vertical active strips is formed between the plurality of stacks. Charge storage structures are formed in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes and the vertical active strips in the plurality of vertical active strips. Gate dielectric, having a different composition than the charge storage structures, is formed in interface regions at cross-points between the vertical active strips and side surfaces of the conductive strips in at least one of the top plane of conductive strips and the bottom plane of conductive strips.