Abstract: A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a stack including first conductive layers and first dielectric layers, a second conductive layer formed on the stack, openings through the second conductive layer and the stack, and through structures formed in the openings, respectively. Each through structure includes a memory layer, a gate dielectric layer, a channel layer, a dielectric material and a pad. The channel layer is isolated from the stack by the memory layer, the channel layer is isolated from the second conductive layer by the gate dielectric layer, and the memory layer and the gate dielectric layer have different compositions.

Abstract: A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a stack including first conductive layers and first dielectric layers, a second conductive layer formed on the stack, openings through the second conductive layer and the stack, and through structures formed in the openings, respectively. Each through structure includes a memory layer, a gate dielectric layer, a channel layer, a dielectric material and a pad. The channel layer is isolated from the stack by the memory layer, the channel layer is isolated from the second conductive layer by the gate dielectric layer, and the memory layer and the gate dielectric layer have different compositions.

Abstract: A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a stack including first conductive layers and first dielectric layers, a second conductive layer formed on the stack, openings through the second conductive layer and the stack, and through structures formed in the openings, respectively. Each through structure includes a memory layer, a gate dielectric layer, a channel layer, a dielectric material and a pad. The channel layer is isolated from the stack by the memory layer, the channel layer is isolated from the second conductive layer by the gate dielectric layer, and the memory layer and the gate dielectric layer have different compositions.

Abstract: A polyurethane-based UV absorber, obtained by reacting a UV absorber having a reactive hydrogen with a polyisocyanate and a diol or polyol; wherein the weight average molecular weight of the polyurethane-based UV absorber is in a range of 10,000 to 200,000.

Abstract: A resistive memory includes a semiconductor substrate, a dielectric layer, an insulating layer and a metal electrode layer. The semiconductor substrate has a top surface and a recess extending downwards into the semiconductor substrate from the top surface. The dielectric layer is disposed on the semiconductor substrate and has a first through-hole aligning the recess. The insulating layer is disposed in the first through-hole and the recess. The metal electrode layer is disposed on the insulating layer by which the metal electrode layer is isolated from the semiconductor substrate.

Abstract: A memory structure includes stacks, memory layers, channel layers, dielectric layers, and first conductive lines. Each stack includes a group of alternating conductive strips and insulating strips. The memory layers are conformally disposed on the stacks. The channel layers are conformally disposed on the memory layers. The dielectric layers are disposed on portions of the channel layers at first sides of the stacks and portions of the channel layers at second sides of the stacks. The first conductive lines are disposed along sidewalls of the stacks. The first conductive lines are isolated from the channel layers by the dielectric layers. One first conductive line disposed at the first side of one stack is isolated from one first conductive line disposed at the second side of the same stack and isolated from one first conductive line disposed at the second side of an adjacent stack.

Abstract: The present invention provides a display device and a backlight module used therein. The backlight module includes a support frame, an optical plate, a load-bearing pin, and an optical film. The support frame encloses an accommodating space. The optical plate is disposed in the accommodating space and has a light-emitting surface and a first end. The load-bearing pin is connected to the support frame and disposed across the light-emitting surface in a position close to the first end. The optical film is disposed corresponding to the light-emitting surface and has a support end and a load-bearing end opposite to each other. The support end is supported by the support frame and the load-bearing end is connected to the first end. The load-bearing pin is located between the optical film and the optical plate and the optical film is held up by the load-bearing pin so that the direction of extension of the optical film is changed.

Abstract: A memory structure and a manufacturing method thereof are provided. The memory structure includes a bottom oxide layer, a first conductive layer on the bottom oxide layer, a first insulation recess, a plurality of insulating layers on the first conductive layer, a plurality of second conductive layers, a second insulation recess, a channel layer on a sidewall of the second insulation recess, and a memory layer located between the channel layer and the second conductive layers. The first insulation recess has a first width and penetrates through the first conductive layer. The second conductive layers and the insulating layers are interlacedly stacked, and the second conductive layers are electrically isolated from the first conductive layer. The second insulation recess located on the first insulation recess has a second width larger than the first width and penetrates through the insulating layers and the second conductive layers.

Abstract: A 3D stacked semiconductor structure is provided, comprising a plurality of stacks vertically formed on a substrate and disposed parallel to each other, a dielectric layer formed on the stacks, a plurality of conductive plugs independently formed in the dielectric layer; and a metal-oxide-semiconductor (MOS) layer formed on the dielectric layer. One of the stacks at least comprises a plurality of multi-layered pillars, and each of the multi-layered pillars comprises a plurality of insulating layers and a plurality of semiconductor layers arranged alternately. The MOS layer comprises a plurality of MOS structures connected to the conductive plugs respectively, and function as layer-selectors for selecting and decoding the to-be-operated layer.

Abstract: A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a stack including first conductive layers and first dielectric layers, a second conductive layer formed on the stack, openings through the second conductive layer and the stack, and through structures formed in the openings, respectively. Each through structure includes a memory layer, a gate dielectric layer, a channel layer, a dielectric material and a pad. The channel layer is isolated from the stack by the memory layer, the channel layer is isolated from the second conductive layer by the gate dielectric layer, and the memory layer and the gate dielectric layer have different compositions.

Abstract: A battery switching method applicable to an electronic device is provided. The electronic device comprises a first battery and a second battery. The method comprises: (a) switching the electronic device to a sleep mode from a normal mode; (b) switching a power supply of the electronic device to the second battery according to a removing signal triggered by removing the first battery; (c) switching the power supply of the electronic device to the first battery according to an inserting signal triggered by inserting the first battery; (d) updating parameters of the first battery; and (e) switching the electronic device to the normal mode from the sleep mode.

Abstract: A sensing device includes a main body, a first battery, a second battery, and a battery switching unit. The first battery includes a power terminal and an ID terminal having a length less than a length of the power terminal. When the battery switching unit detects that the power terminal and the ID terminal are both electrically connected to a connector positioned in the main body, the battery switching unit switches to the first battery and the sensing device is powered by the first battery; when the battery switching unit detects that the ID terminal is just disconnected with the connector, the first battery keeps providing power to the sensing device through the power terminal and the battery switching unit switches to the second battery so that the sensing device is powered by the second battery before the power terminal being disconnected with the connector.

Abstract: A 3D semiconductor memory device includes a semiconductor substrate, a source line, a gate line and a plurality of memory cells connected in series. The semiconductor substrate has a protruding portion. The source line is disposed in the semiconductor substrate and partially extending below the protruding portion. The gate line is configured to surround and cover the protruding portion and electrically separated from the source line and the protruding portion. The memory cells are disposed on the semiconductor substrate and connected in series to the protruding portion at a top surface thereof.

Abstract: A memory device includes a semiconductor substrate, an isolation layer disposed on the semiconductor substrate, a first conductive layer disposed on the isolation layer, at least one contact plug passing through the isolation layer and electrically contacting the semiconductor substrate with the first conductive layer, a plurality of insulating layers disposed on the first conductive layer, a plurality of second conductive layers alternatively stacked with the insulating layers and insulated from the first conductive layer, a channel layer disposed on at least one sidewall of a first through opening and electrically contacting to the contact plug, wherein the first through opening passes through the insulating layers and the second conductive layers to expose the contact plug, and a memory layer disposed between the channel layer and the second conductive layers.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, stacks, a blocking layer-trapping layer-tunneling layer structure, channel layers, a first insulating material and a dielectric layer. The stacks are formed on the substrate. Each stack comprises a group of alternating conductive strips and insulating strips as well as a first string select line formed on the group. The blocking layer-trapping layer-tunneling layer structure and the channel layers are formed conformally with the stacks. The first insulating material is formed between the stacks and covers portions of the channel layers. The dielectric layer is formed on portions of the channel layers that are not covered by the first insulating material. The semiconductor structure further comprises second string select lines formed between the stacks on the first insulating material, wherein the second string select lines are separated from the channel layers by the dielectric layer.

Abstract: A memory device having an array area and a periphery area is provided. The memory device includes a substrate, an isolation layer formed in the substrate, a first doped region formed on the isolation layer in the array area, a second doped region formed on the first doped region, a metal silicide layer formed on the second doped region, and a metal silicide oxide layer formed on the metal silicide layer.

Abstract: A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. Two stacked structures are formed a substrate. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers and a top insulating layer. A charge trapping structure and a channel layer are formed. The charge trapping structure includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched and part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the first dielectric layers and the second dielectric layers to connect the channel layer.

Abstract: A memory device is provided. The memory device includes a substrate, a plurality of alternately stacked semiconductor layers and oxide layers disposed on the substrate, at least one through hole penetrating the stacked semiconductor layers and oxide layers, and an electrode layer disposed in the through hole. Each of the semiconductor layers includes a first area having a first conductive type and a second area having a second conductive type opposite to the first conductive type.

Abstract: A memory device includes an array of strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. A plurality of vertical active strips is formed between the plurality of stacks. Charge storage structures are formed in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes and the vertical active strips in the plurality of vertical active strips. Gate dielectric, having a different composition than the charge storage structures, is formed in interface regions at cross-points between the vertical active strips and side surfaces of the conductive strips in at least one of the top plane of conductive strips and the bottom plane of conductive strips.

Abstract: A memory device includes a semiconductor substrate, an isolation layer disposed on the semiconductor substrate, a first conductive layer disposed on the isolation layer, at least one contact plug passing through the isolation layer and electrically contacting the semiconductor substrate with the first conductive layer, a plurality of insulating layers disposed on the first conductive layer, a plurality of second conductive layers alternatively stacked with the insulating layers and insulated from the first conductive layer, a channel layer disposed on at least one sidewall of a first through opening and electrically contacting to the contact plug, wherein the first through opening passes through the insulating layers and the second conductive layers to expose the contact plug, and a memory layer disposed between the channel layer and the second conductive layers.