Abstract: An acid dye composition for dyeing nylon textiles is disclosed, which comprises: an acid dye; and a water soluble Ca2+ compound, wherein, on the basis of a total weight of the acid dye as 100 parts by weight, a content of the water soluble Ca2+ compound is ranged from 0.1 parts by weight to 50 parts by weight. In addition, a use of the aforesaid acid dye composition and a method using the same for dyeing nylon textiles are also disclosed.

Abstract: A memory device memory device includes a multi-layers stack, a charge-trapping layer, a first channel layer and a SSL switch. The multi-layers stack includes a plurality of insulating layers, a plurality of conductive layers alternatively stacked with the insulating layers and at least one first through opening passing through the conductive layers. The charge-trapping layer blankets over a sidewall of the first through opening. The first channel layer is disposed in the first through opening. The SSL switch is disposed on the multi-layers stack and includes a second channel layer, a gate dielectric layer and a gate. The second channel layer is disposed on and electrically contacting to the first channel layer. The gate dielectric layer is disposed on the second channel layer and made of a material other than that for making the charge-trapping layer. The gate is disposed on the gate dielectric layer.

Abstract: A 3D semiconductor memory device includes a semiconductor substrate, a source line, a gate line and a plurality of memory cells connected in series. The semiconductor substrate has a protruding portion. The source line is disposed in the semiconductor substrate and partially extending below the protruding portion. The gate line is configured to surround and cover the protruding portion and electrically separated from the source line and the protruding portion. The memory cells are disposed on the semiconductor substrate and connected in series to the protruding portion at a top surface thereof.

Abstract: A 3D memory device includes a substrate, a multi-layers stack, at least one memory structure and an etching stop structure. The substrate has a trench. The multi-layers stack includes a first extending portion forming a non-straight angle with a bottom surface of the trench and a second extending portion, wherein both of the first extending portion and the second extending portion include a plurality of conductive layers and a plurality of insulating layers alternatively stacked in the trench. The memory structure is formed in the first extending portion. The etching stop structure is at least partially disposed in the second extending portion and has a material identical to that of the memory structure.

Abstract: A 3D semiconductor memory device includes a semiconductor substrate, a source line, a gate line and a plurality of memory cells connected in series. The semiconductor substrate has a protruding portion. The source line is disposed in the semiconductor substrate and partially extending below the protruding portion. The gate line is configured to surround and cover the protruding portion and electrically separated from the source line and the protruding portion. The memory cells are disposed on the semiconductor substrate and connected in series to the protruding portion at a top surface thereof.

Abstract: A memory device memory device includes a multi-layers stack, a charge-trapping layer, a first channel layer and a SSL switch. The multi-layers stack includes a plurality of insulating layers, a plurality of conductive layers alternatively stacked with the insulating layers and at least one first through opening passing through the conductive layers. The charge-trapping layer blankets over a sidewall of the first through opening. The first channel layer is disposed in the first through opening. The SSL switch is disposed on the multi-layers stack and includes a second channel layer, a gate dielectric layer and a gate. The second channel layer is disposed on and electrically contacting to the first channel layer. The gate dielectric layer is disposed on the second channel layer and made of a material other than that for making the charge-trapping layer. The gate is disposed on the gate dielectric layer.

Abstract: A semiconductor device includes a substrate and a memory structure disposed above the substrate. An embodied memory structure includes a bottom electrode disposed above the substrate, a barrier layer disposed at the bottom electrode, a resistance switching layer disposed on the bottom electrode and above the barrier layer, and a top electrode disposed on the resistance switching layer and covering the resistance switching layer. A bottom surface of the resistance switching layer is spaced apart from an uppermost surface of the barrier layer by a distance.

Abstract: A method of manufacturing a three-dimensional (3D) stacked semiconductor structure is provided. A multi-layered stack is formed above a substrate, and the multi-layered stack comprises a plurality of nitride layers and polysilicon layers arranged alternately. Several channel holes are formed vertically to the substrate. The multi-layered stack is patterned to form linear spaces between the channel holes, wherein the linear spaces extend downwardly for being vertical to the substrate and to expose sidewalls of the nitride layers and the polysilicon layers. Then, the polysilicon layers are replaced with insulating layers having air-gaps through the linear spaces, and the nitride layers are replaced with conductive layers through the linear spaces.

Abstract: A memory device memory device includes a multi-layers stack, a charge-trapping layer, a first channel layer and a SSL switch. The multi-layers stack includes a plurality of insulating layers, a plurality of conductive layers alternatively stacked with the insulating layers and at least one first through opening passing through the conductive layers. The charge-trapping layer blankets over a sidewall of the first through opening. The first channel layer is disposed in the first through opening. The SSL switch is disposed on the multi-layers stack and includes a second channel layer, a gate dielectric layer and a gate. The second channel layer is disposed on and electrically contacting to the first channel layer. The gate dielectric layer is disposed on the second channel layer and made of a material other than that for making the charge-trapping layer. The gate is disposed on the gate dielectric layer.

Abstract: The present invention provides a display device and a backlight module used therein. The backlight module includes a support frame, an optical plate, a load-bearing pin, and an optical film. The support frame encloses an accommodating space. The optical plate is disposed in the accommodating space and has a light-emitting surface and a first end. The load-bearing pin is connected to the support frame and disposed across the light-emitting surface in a position close to the first end. The optical film is disposed corresponding to the light-emitting surface and has a support end and a load-bearing end opposite to each other. The support end is supported by the support frame and the load-bearing end is connected to the first end. The load-bearing pin is located between the optical film and the optical plate and the optical film is held up by the load-bearing pin so that the direction of extension of the optical film is changed.

Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: forming a bottom oxide layer; forming a first conductive layer on the bottom oxide layer; forming a stack including alternately arranged second conductive layers and insulating layers on the first conductive layer; forming a first opening having a first cross-sectional width and penetrating through the stack and a portion of the first conductive layer; forming a second opening having a second cross-sectional width and penetrating through the first conductive layer below the first opening for exposing the bottom oxide layer, wherein the second cross-sectional width is smaller than the first cross-sectional width; and forming a memory layer on a sidewall of the first opening and filled in the second opening.

Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: forming a bottom oxide layer; forming a first conductive layer on the bottom oxide layer; forming a stack including alternately arranged second conductive layers and insulating layers on the first conductive layer; forming a first opening having a first cross-sectional width and penetrating through the stack and a portion of the first conductive layer; forming a second opening having a second cross-sectional width and penetrating through the first conductive layer below the first opening for exposing the bottom oxide layer, wherein the second cross-sectional width is smaller than the first cross-sectional width; and forming a memory layer on a sidewall of the first opening and filled in the second opening.

Abstract: A memory structure includes a substrate, a plurality of stacks, a plurality of memory layers, a plurality of channel layers and a plurality of pad layers. The stacks are disposed on the substrate. The stacks are separated from each other by a plurality of first trenches. The stacks include alternately arranged first stacks and second stacks. Each of the stacks includes alternately stacked conductive strips and insulating strips. The memory layers are partially disposed in the first trenches. The memory layers extend onto the stacks in a conformal manner. The channel layers are disposed on the memory layers in a conformal manner. The pad layers are at least disposed on the channel layers at positions substantially above the first stacks.

Abstract: A memory structure includes a substrate, a plurality of stacks, a plurality of memory layers, a plurality of channel layers and a plurality of pad layers. The stacks are disposed on the substrate. The stacks are separated from each other by a plurality of first trenches. The stacks include alternately arranged first stacks and second stacks. Each of the stacks includes alternately stacked conductive strips and insulating strips. The memory layers are partially disposed in the first trenches. The memory layers extend onto the stacks in a conformal manner. The channel layers are disposed on the memory layers in a conformal manner. The pad layers are at least disposed on the channel layers at positions substantially above the first stacks.

Abstract: A 3D memory device includes a plurality of vertical pillars composed of a vertical channel and a multilayer data storage structure. The multilayer data storage structure can comprise a dielectric charge trapping structure. A stack of dielectric lined conductive strips separated in the stack by insulating strips have sidewalls disposed adjacent the corresponding vertical pillars. The conductive strips have a dielectric liner having a dielectric constant ? greater than 7 on the sidewalls in contact with the outside layer of the multilayer data storage structure on the corresponding pillar. The conductive strips in embodiments described herein can comprise a relatively low resistance material, such as a metal or a metal nitride. A manufacturing method using Si—Ge selective etching of sacrificial layers can be used in a gate replacement process to form the dielectric conductive strips.

Abstract: A memory device includes a peripheral circuit portion and an array portion disposed on the peripheral circuit portion. The array portion includes a bottom conductive layer; an isolation layer disposed on the bottom conductive layer; a semiconductor substrate disposed on the isolation layer; a channel layer disposed on a sidewall of a first through opening which exposes the semiconductor substrate and electrically contacting the semiconductor substrate; a memory layer; and a multilayers stack disposed on the semiconductor substrate. The multilayers stack includes a first insulating layer disposed on the semiconductor substrate; a first conductive layer disposed on the first insulating layer; second insulating layers disposed over the first insulating layer; and second conductive layers alternatively stacked with the second insulating layers and insulated from the first conductive layer.

Abstract: A polyurethane-based UV absorber, obtained by reacting a UV absorber having a reactive hydrogen with a polyisocyanate and a diol or polyol; wherein the weight average molecular weight of the polyurethane-based UV absorber is in a range of 10,000 to 200,000.

Abstract: A sensing device includes a main body, a first battery, a second battery, and a battery switching unit. The first battery includes a power terminal and an ID terminal having a length less than a length of the power terminal. When the battery switching unit detects that the power terminal and the ID terminal are both electrically connected to a connector positioned in the main body, the battery switching unit switches to the first battery and the sensing device is powered by the first battery; when the battery switching unit detects that the ID terminal is just disconnected with the connector, the first battery keeps providing power to the sensing device through the power terminal and the battery switching unit switches to the second battery so that the sensing device is powered by the second battery before the power terminal being disconnected with the connector.

Abstract: A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a stack including first conductive layers and first dielectric layers, a second conductive layer formed on the stack, openings through the second conductive layer and the stack, and through structures formed in the openings, respectively. Each through structure includes a memory layer, a gate dielectric layer, a channel layer, a dielectric material and a pad. The channel layer is isolated from the stack by the memory layer, the channel layer is isolated from the second conductive layer by the gate dielectric layer, and the memory layer and the gate dielectric layer have different compositions.

Abstract: Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer Arrays and methods of operation are described.