Patents by Inventor Kun-tack Lee

Kun-tack Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160071745
    Abstract: A spot heater and a device for cleaning a wafer using the same are provided. The wafer cleaning device includes a heater chuck on which a wafer is mounted, the heater chuck configured to heat a bottom surface of the wafer; a chemical liquid nozzle configured to spray a chemical liquid on a top surface of the wafer for etching; and a spot heater configured to heat a spot of the top surface of the wafer.
    Type: Application
    Filed: May 7, 2015
    Publication date: March 10, 2016
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Hoo KIM, Il-Sang LEE, Yong-sun KO, Chang-Gil RYU, Kun-Tack LEE, Hyo-San LEE
  • Publication number: 20150299629
    Abstract: A cleaning solution composition includes an organic solvent in which a metal fluoride does not dissolve, at least one fluoride compound that generates bifluoride (HF2?), and deionized water, wherein the deionized water may be included in a concentration of 1.5 wt % or lower based on the total weight of the cleaning solution composition.
    Type: Application
    Filed: November 17, 2014
    Publication date: October 22, 2015
    Inventors: Sang-Won Bae, Yong-Sun Ko, Seok-Hoon Kim, In-Gi Kim, Jung-Min Oh, Kun-Tack Lee, Hyo-San Lee, Ji-Hoon Jeong, Yong-Jhin Cho
  • Publication number: 20150176897
    Abstract: A sealing member includes a body having a ring shape, a lower contacting portion protruding from a lower end of the body and having at least one recess, the recess provided in a lower surface of the lower contacting portion and extending in a radial direction of the body, and an outer contacting portion protruding outwards from the body along an outer side portion of the body.
    Type: Application
    Filed: December 1, 2014
    Publication date: June 25, 2015
    Inventors: Yong-Myung JUN, Yong-Sun KO, Kun-Tack LEE, Il-Sang LEE, Ji-Hoon JEONG, Yong-Jhin CHO, Jin-Suk HONG
  • Publication number: 20150162221
    Abstract: Provided are an apparatus and method for treating wafers using a supercritical fluid. The wafer treatment apparatus includes a plurality of chambers; a first supply supplying a first fluid in a supercritical state; a second supply supplying a mixture of the first fluid and a second fluid; a plurality of first and second valves; and a controller selecting a first chamber of the plurality of chambers for wafer treatment to control the open/closed state of each of the plurality of first valves so that the first fluid can be supplied only to the first chamber of the plurality of chambers and selecting a second chamber of the plurality of chambers to control the open/closed state of each of the plurality of second valves so that the mixture of the first fluid and a second fluid can be supplied only to the second chamber of the plurality of chambers.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 11, 2015
    Inventors: Hyo-San Lee, Chang-ki Hong, Kun-tack Lee, Jeong-nam Han
  • Publication number: 20150151336
    Abstract: A nozzle may include a nozzle body, a conductive line and a resistance-measuring member. The nozzle body may include a plurality of injecting holes. The conductive line may be disposed along the injecting holes. The resistance-measuring member may be configured to measure a resistance of the conductive line to detect a deformation of the injecting holes.
    Type: Application
    Filed: June 11, 2014
    Publication date: June 4, 2015
    Inventors: KYOUNG-SEOB KIM, SUCK-HYUN KANG, YONG-SUN KO, KYOUNG-HWAN KIM, KUN-TACK LEE, HYO-SAN LEE
  • Patent number: 8951383
    Abstract: Provided are an apparatus and method for treating wafers using a supercritical fluid. The wafer treatment apparatus includes a plurality of chambers; a first supply supplying a first fluid in a supercritical state; a second supply supplying a mixture of the first fluid and a second fluid; a plurality of first and second valves; and a controller selecting a first chamber of the plurality of chambers for wafer treatment to control the open/closed state of each of the plurality of first valves so that the first fluid can be supplied only to the first chamber of the plurality of chambers and selecting a second chamber of the plurality of chambers to control the open/closed state of each of the plurality of second valves so that the mixture of the first fluid and a second fluid can be supplied only to the second chamber of the plurality of chambers.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-san Lee, Chang-ki Hong, Kun-tack Lee, Jeong-nam Han
  • Publication number: 20140283886
    Abstract: In a supercritical fluid method a supercritical fluid is supplied into a process chamber. The supercritical fluid is discharged from the process chamber as a supercritical fluid process proceeds. A concentration of a target material included in the supercritical fluid discharged from the process chamber is detected during the supercritical fluid process. An end point of the supercritical fluid process may be determined based on a detected concentration of the target material.
    Type: Application
    Filed: June 6, 2014
    Publication date: September 25, 2014
    Inventors: Yong-Jhin CHO, Kun-Tack LEE, Hyo-San LEE, Young-Hoo KIM, Jung-Won LEE, Sang-Won BAE, Jung-Min HO
  • Patent number: 8795541
    Abstract: In a supercritical fluid method a supercritical fluid is supplied into a process chamber. The supercritical fluid is discharged from the process chamber as a supercritical fluid process proceeds. A concentration of a target material included in the supercritical fluid discharged from the process chamber is detected during the supercritical fluid process. An end point of the supercritical fluid process may be determined based on a detected concentration of the target material.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: August 5, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Jhin Cho, Kun-Tack Lee, Hyo-San Lee, Young-Hoo Kim, Jung-Won Lee, Sang-Won Bae, Jung-Min Oh
  • Patent number: 8790470
    Abstract: Provided herein are etching, cleaning and drying methods using a supercritical fluid, and a chamber system for conducting the same. The etching method includes etching the material layer using a supercritical carbon dioxide in which an etching chemical is dissolved, and removing an etching by-product created from a reaction between the material layer and the etching chemical using a supercritical carbon dioxide in which a cleaning chemical is dissolved. Methods of manufacturing a semiconductor device are also provided.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-san Lee, Chang-Ki Hong, Kun-Tack Lee, Woo-Gwan Shim, Jeong-Nam Han, Jung-Min Oh, Kwon-Taek Lim, Ha-Soo Hwang, Haldorai Yuvaraj, Jae-Mok Jung
  • Patent number: 8766343
    Abstract: In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: July 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Hyuk Kang, Bo-Un Yoon, Kun-Tack Lee, Woo-Gwan Shim, Ji-Hoon Cha, Im-Soo Park, Hyo-San Lee, Young-Hoo Kim, Jung-Min Oh
  • Patent number: 8597081
    Abstract: A pad conditioning disk, a pre-conditioning unit, and a CMP apparatus having the same are provided. The pad conditioning disk includes a base in which mountain-type tips and valley-type grooves are repeatedly connected to each other, and a cutting layer formed on the base layer. The cutting layer including conditioning particles deposited on surfaces of the tips and grooves. A surfaces roughness of conditioning particles deposited on the surfaces of the tips is less than a surface roughness of conditioning particles deposited on the surfaces of the grooves.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Kwang Choi, Hong-Jin Kim, Keon-Sik Seo, Sol Han, Kun-Tack Lee, Byoung-Ho Kwon
  • Patent number: 8585917
    Abstract: Provided herein are etching, cleaning and drying methods using a supercritical fluid, and a chamber system for conducting the same. The etching method includes etching the material layer using a supercritical carbon dioxide in which an etching chemical is dissolved, and removing an etching by-product created from a reaction between the material layer and the etching chemical using a supercritical carbon dioxide in which a cleaning chemical is dissolved. Methods of manufacturing a semiconductor device are also provided.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: November 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-san Lee, Chang-Ki Hong, Kun-Tack Lee, Woo-Gwan Shim, Jeong-Nam Han, Jung-Min Oh, Kwon-Taek Lim, Ha-Soo Hwang, Haldorai Yuvaraj, Jae-Mok Jung
  • Patent number: 8557651
    Abstract: In an etchant for etching a capping layer having etching selectivity with respect to a dielectric layer, the capping layer changes compositions of the dielectric layer, to thereby control a threshold voltage of a gate electrode including the dielectric layer. The etchant includes about 0.01 to 3 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt and a solvent. Accordingly, the dielectric layer is prevented from being damaged by the etching process for removing the capping layer and the electric characteristics of the gate electrode are improved.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-San Lee, Bo-Un Yoon, Kun-Tack Lee, Hag-Ju Cho, Sang-Jin Hyun, Hoon-Joo Na, Hyung-Seok Hong
  • Patent number: 8524569
    Abstract: In a method of forming an isolation layer, first and second trenches are formed on a substrate. The first and the second trenches have first and second widths, respectively, and the second width is greater than the first width. A second isolation layer pattern partially fills the second trench. A first isolation layer pattern and the third isolation layer pattern are formed. The first isolation layer pattern fills the first trench, and the third isolation layer pattern is formed on the second isolation layer pattern and fills a remaining portion of the second trench.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: September 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Hyuk Kang, Jung-Won Lee, Bo-Un Yoon, Kun-Tack Lee
  • Patent number: 8344385
    Abstract: In a vertical-type non-volatile memory device, an insulation layer pattern is provided on a substrate, the insulation layer pattern having a linear shape. Single-crystalline semiconductor patterns are provided on the substrate to make contact with both sidewalls of the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate. A tunnel oxide layer is provided on the single-crystalline semiconductor pattern. A lower electrode layer pattern is provided on the tunnel oxide layer and on the substrate. A plurality of insulation interlayer patterns is provided on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a predetermined distance along the single-crystalline semiconductor pattern. A charge-trapping layer and a blocking dielectric layer are sequentially formed on the tunnel oxide layer between the insulation interlayer patterns.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hoo Kim, Hyo-San Lee, Sang-Won Bae, Bo-Un Yoon, Kun-Tack Lee
  • Patent number: 8211804
    Abstract: In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the preliminary hole. An etching gas including hydrogen fluoride (HF) or fluorine (F2) is then provided onto the photosensitive layer pattern to etch the insulation layer so that width of the preliminary hole is increased.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: July 3, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-San Lee, Bo-Un Yoon, Kun-Tack Lee, Dae-Hyuk Kang, Seong-Ho Moon, So-Ra Han
  • Publication number: 20120152898
    Abstract: In a supercritical fluid method a supercritical fluid is supplied into a process chamber. The supercritical fluid is discharged from the process chamber as a supercritical fluid process proceeds. A concentration of a target material included in the supercritical fluid discharged from the process chamber is detected during the supercritical fluid process. An end point of the supercritical fluid process may be determined based on a detected concentration of the target material.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 21, 2012
    Inventors: YONG JHIN CHO, Kun-Tack LEE, Hyo-San LEE, Young-Hoo KIM, Jung-Won LEE, Sang-Won BAE, Jung-Min OH
  • Publication number: 20120112317
    Abstract: In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
    Type: Application
    Filed: January 23, 2012
    Publication date: May 10, 2012
    Inventors: Dae-Hyuk Kang, Bo-Un Yoon, Kun-Tack Lee, Woo-Gwan Shim, Ji-Hoon Cha, Im-Soo Park, Hyo-San Lee, Young-Hoo Kim, Jung-Min Oh
  • Publication number: 20120085495
    Abstract: Provided herein are etching, cleaning and drying methods using a supercritical fluid, and a chamber system for conducting the same. The etching method includes etching the material layer using a supercritical carbon dioxide in which an etching chemical is dissolved, and removing an etching by-product created from a reaction between the material layer and the etching chemical using a supercritical carbon dioxide in which a cleaning chemical is dissolved. Methods of manufacturing a semiconductor device are also provided.
    Type: Application
    Filed: December 15, 2011
    Publication date: April 12, 2012
    Inventors: Hyo-San Lee, Chang-Ki Hong, Kun-Tack Lee, Woo-Gwan Shim, Jeong-Nam Han, Jung-Min Oh, Kwon-Tack Lim, Ha-Soo Hwang, Haldori Vuvaraj, Jae-Monk Jung
  • Publication number: 20120083189
    Abstract: A pad conditioning disk, a pre-conditioning unit, and a CMP apparatus having the same are provided. The pad conditioning disk includes a base in which mountain-type tips and valley-type grooves are repeatedly connected to each other, and a cutting layer formed on the base layer. The cutting layer including conditioning particles deposited on surfaces of the tips and grooves. A surfaces roughness of conditioning particles deposited on the surfaces of the tips is less than a surface roughness of conditioning particles deposited on the surfaces of the grooves.
    Type: Application
    Filed: September 23, 2011
    Publication date: April 5, 2012
    Inventors: Jae-Kwang Choi, Hong-Jin Kim, Keon-Sik Seo, Sol Han, Kun-Tack Lee, Byoung-Ho Kwon