Patents by Inventor Kun Tian

Kun Tian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12008081
    Abstract: A method, a computing system and a computer program product for collecting and labelling images includes capturing a video of an object with a camera. A movement trace of a pointer is recorded that outlines the object while capturing the video of the object. Further included is generating a labeled image based at least on the captured video of the object and the recorded movement trace of the pointer. The labeled image includes the object and a line that surrounds the object.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: June 11, 2024
    Assignee: International Business Machines Corporation
    Inventors: Tian Tian Chai, Hong Bing Zhang, Kun Yan Yin, Miao Guo, Yu Luo, Yun Jing Zhao
  • Publication number: 20240179597
    Abstract: An electronic device, a wireless communication method, and a computer readable storage medium are provided. The electronic device comprises a processing circuit configured to: determine whether uplink transmission of an IAB node satisfies a long-term congestion condition; when it is determined that the long-term congestion condition is satisfied, send an offloading request to an IAB donor node; and perform data offloading of an egress link of the uplink transmission of the IAB node according to offloading license information from the IAB donor node. According to at least one aspect of the embodiments of the present disclosure, when the uplink transmission of the IAB node satisfies the long-term congestion condition, the data offloading of the egress link of the uplink transmission of the IAB node can be performed, so as to improve the backhaul capability of the IAB node, thereby solving the long-term congestion problem of the IAB node.
    Type: Application
    Filed: February 23, 2022
    Publication date: May 30, 2024
    Applicant: Sony Group Corporation
    Inventors: Xiaodong XU, Kun LI, Shiying YAN, Zhihan HUANG, Lu TIAN, Shumeng ZHANG, Haojin LI, Tao CUI
  • Patent number: 11995462
    Abstract: Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: May 28, 2024
    Assignee: Intel Corporation
    Inventors: Sanjay Kumar, Philip R. Lantz, Kun Tian, Utkarsh Y. Kakaiya, Rajesh M. Sankaran
  • Publication number: 20240146868
    Abstract: Embodiments of this disclosure relate to the multimedia processing field, and provide a video frame interpolation method, apparatus, and a device. In the video frame interpolation method in this disclosure, a first image at first time, a second image at second time, and sensor data captured by a dynamic vision sensor apparatus are obtained, and the sensor data includes dynamic event data between the first time and the second time. At least one target image is determined based on the first image, the second image, and the sensor data, where the at least one target image is an image corresponding to at least one target time between the first time and the second time. The dynamic event data is used to help compensate for motion information missing from existing image data. This implements accurate prediction of an intermediate image, and improves image prediction effect.
    Type: Application
    Filed: December 20, 2023
    Publication date: May 2, 2024
    Inventors: Ziyang ZHANG, Weihua HE, Chen YANG, Jianxing LIAO, Kun TIAN, Ying WANG, Yunlong ZHAN
  • Patent number: 11971827
    Abstract: Methods, apparatus, systems and articles of manufacture to control address space isolation in a virtual machine are disclosed. An example apparatus includes an address width adjustor to identify a memory width value corresponding to a guest memory associated with a virtual machine (VM), and generate an expanded emulated memory width value. The example apparatus also includes a memory mirror manager to generate a first guest physical address (GPA) range based on the memory width value, and generate a second GPA range based on the expanded emulated memory width value. The example apparatus also includes an EPT generator to generate root paging structures of a first type of EPT with respective addresses within the first GPA range, and generate root paging structures of a second type of EPT with respective addresses within (a) the first GPA range and (b) the second GPA range.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: April 30, 2024
    Assignee: Intel Corporation
    Inventors: Jun Tian, Kun Tian, Yu Zhang
  • Publication number: 20240137547
    Abstract: A data processing method includes receiving an event data stream, where the event data stream includes at least a first event data item and a second event data item, the first event data item includes a first timestamp for obtaining the first event data item, the second event data item includes a second timestamp for obtaining the second event data item, and the second event data item is obtained most recently before obtaining the first event data item; and obtaining a compressed event data stream corresponding to the event data stream, where the compressed event data stream includes at least a first compressed event data item corresponding to the first event data item, and the first compressed event data item includes first time information.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 25, 2024
    Inventors: Ziyang Zhang, Yaozhun Huang, Xuxu Li, Lindong Wu, Weihua He, Kun Tian, Jianxing Liao, Ying Wang, Yaoyuan Wang
  • Publication number: 20240126695
    Abstract: Various embodiments are generally directed to virtualized systems. A first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (VM) on the processor, the first guest memory page corresponding to a first byte-addressable memory. The execution of the VM and the application on the processor may be paused. The first guest memory page may be migrated to a target memory page in a second byte-addressable memory, the target memory page comprising one of a target host memory page and a target guest memory page, the second byte-addressable memory having an access speed faster than an access speed of the first byte-addressable memory.
    Type: Application
    Filed: December 21, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Yao Zu DONG, Kun TIAN, Fengguang WU, Jingqi LIU
  • Patent number: 11960422
    Abstract: Systems, apparatuses and methods may provide for a frontend driver that notifies a hypervisor of a map request from a guest driver of a device, wherein the device is passed through to and directly controlled by a virtual machine, and wherein the map request is associated with an attempt of the device to access a guest memory page in a virtualized execution environment. The frontend driver may also determine whether the guest memory page is pinned and send a map hypercall to the hypervisor if the guest memory page is not pinned. Additionally, the hypervisor may determine that the guest memory page is pinned, determine, based on a direct memory access (DMA) bitmap, that an unmap request from the guest driver has been issued, and unpin the guest memory page.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: April 16, 2024
    Assignee: Intel Corporation
    Inventors: Kun Tian, Yan Zhao, Yu Zhang
  • Patent number: 11947991
    Abstract: A disclosed example includes accessing, by a backend block service driver in an input/output virtual machine executing on one or more processors, a first command submitted to a buffer by a paravirtualized input/output frontend block driver executing in a guest virtual machine; generating, by the backend block service driver, a translated command based on the first command by translating a virtual parameter of the first command to a physical parameter associated with a physical resource; submitting, by the backend block service driver, the translated command to an input/output queue to be processed by the physical resource based on the physical parameter; and submitting, by the backend block service driver, a completion status entry to the buffer, the completion status entry indicative of completion of a direct memory access operation that copies data between the physical resource and a guest memory buffer corresponding to the guest virtual machine.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Yao Zu Dong, Yuankai Guo, Haozhong Zhang, Kun Tian
  • Patent number: 11933835
    Abstract: The present invention relates to the technical field of fault location of distributed energy resources connected flexible DC distribution network, and disclosed a fault location method, system and application of bipolar short-circuit of two-level VSC-type photovoltaic-connected flexible DC distribution network, wherein, directions of positive currents of DC feeders during fault are used to locate a fault section; a bipolar short-circuit distance measurement model covering interactions and responses of systems is established according to equivalent circuits of transient periods; and fault location is done by obtaining a distance to fault with electric parameters and information of the fault.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: March 19, 2024
    Assignee: CHINA UNIVERSITY OF PETROLEUM (EAST CHINA)
    Inventors: Zhihua Zhang, Mingming Sun, Yongtao Tian, Hao Wang, Kun Wang, Chengmin Liu
  • Patent number: 11921632
    Abstract: Various embodiments are generally directed to virtualized systems. A first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (VM) on the processor, the first guest memory page corresponding to a first byte-addressable memory. The execution of the VM and the application on the processor may be paused. The first guest memory page may be migrated to a target memory page in a second byte-addressable memory, the target memory page comprising one of a target host memory page and a target guest memory page, the second byte-addressable memory having an access speed faster than an access speed of the first byte-addressable memory.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Yao Zu Dong, Kun Tian, Fengguang Wu, Jingqi Liu
  • Publication number: 20240012735
    Abstract: In an embodiment, a processor for redirecting requests includes a processing engine to execute a guest system, and monitoring circuitry coupled to the processing engine. The monitoring circuitry may be to: receive, from the guest system, a first request to access a first virtual counter; in response to a receipt of the first request, determine, based a mapping register of the processor, a first physical counter mapped to the first virtual counter; and redirect the first request to the first physical counter mapped to the first virtual counter. Other embodiments are described and claimed.
    Type: Application
    Filed: December 24, 2020
    Publication date: January 11, 2024
    Inventors: Wei Wang, Matthew Merten, Beeman Strong, Andreas Kleen, Kan Liang, Gilbert Neiger, Kun Tian, Like Xu
  • Publication number: 20230418762
    Abstract: Embodiments of apparatuses, methods, and systems for unified address translation for virtualization of input/output devices are described. In an embodiment, an apparatus includes first circuitry to use at least an identifier of a device to locate a context entry and second circuitry to use at least a process address space identifier (PASID) to locate a PASID-entry. The context entry is to include at least one of a page-table pointer to a page-table translation structure and a PASID. The PASID-entry is to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second-level translation structure. The PASID is to be supplied by the device. At least one of the apparatus, the context entry, and the PASID entry is to include one or more control fields to indicate whether the first-level page-table pointer or the second-level page-table pointer is to be used.
    Type: Application
    Filed: May 22, 2023
    Publication date: December 28, 2023
    Applicant: Intel Corporation
    Inventors: Utkarsh Y. Kakaiya, Sanjay Kumar, Rajesh M. Sankaran, Philip R. Lantz, Ashok Raj, Kun Tian
  • Patent number: 11768781
    Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: September 26, 2023
    Assignee: Intel Corporation
    Inventors: Niranjan L. Cooray, Abhishek R. Appu, Altug Koker, Joydeep Ray, Balaji Vembu, Pattabhiraman K, David Puffer, David J. Cowperthwaite, Rajesh M. Sankaran, Satyeshwar Singh, Sameer Kp, Ankur N. Shah, Kun Tian
  • Patent number: 11734209
    Abstract: Implementations of the disclosure provide processing device comprising: an interrupt managing circuit to receive an interrupt message directed to an application container from an assignable interface (AI) of an input/output (I/O) device. The interrupt message comprises an address space identifier (ASID), an interrupt handle and a flag to distinguish the interrupt message from a direct memory access (DMA) message. Responsive to receiving the interrupt message, a data structure associated with the interrupt managing circuit is identified. An interrupt entry from the data structure is selected based on the interrupt handle. It is determined that the ASID associated with the interrupt message matches an ASID in the interrupt entry. Thereupon, an interrupt in the interrupt entry is forwarded to the application container.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Sanjay Kumar, Rajesh M. Sankaran, Philip R. Lantz, Utkarsh Y. Kakaiya, Kun Tian
  • Publication number: 20230259884
    Abstract: Described herein is a technique for deriving and using a member profile-to-job posting graph that includes a plurality of implicit facets that map member profiles to job postings. Each implicit facet is a combination of member profile attributes linked with job profile attributes, such that a member profile is linked to the implicit facet when the member profile has member profile attribute values that match those of the implicit facet, and a job posting is linked to the implicit facet when the job posting has job attribute values that match those of the implicit facet. Using the graph, information about the potential applicant pool for a new job posting can be derived and presented to the person who is creating the new job posting.
    Type: Application
    Filed: February 17, 2022
    Publication date: August 17, 2023
    Inventors: Wen Pu, Yuchin Juan, Ping Liu, Kun Tian, Dawei Wang
  • Publication number: 20230251912
    Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Applicant: Intel Corporation
    Inventors: Utkarsh Y. KAKAIYA, Rajesh SANKARAN, Sanjay KUMAR, Kun TIAN, Philip LANTZ
  • Patent number: 11715174
    Abstract: Embodiments described herein provide techniques enable a graphics processor to continue processing operations during the reset of a compute unit that has experienced a hardware fault. Threads and associated context state for a faulted compute unit can be migrated to another compute unit of the graphics processor and the faulting compute unit can be reset while processing operations continue.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: August 1, 2023
    Assignee: Intel Corporation
    Inventors: Murali Ramadoss, Balaji Vembu, Eric C. Samson, Kun Tian, David J. Cowperthwaite, Altug Koker, Zhi Wang, Joydeep Ray, Subramaniam M. Maiyuran, Abhishek R. Appu
  • Patent number: 11698866
    Abstract: Embodiments of apparatuses, methods, and systems for unified address translation for virtualization of input/output devices are described. In an embodiment, an apparatus includes first circuitry to use at least an identifier of a device to locate a context entry and second circuitry to use at least a process address space identifier (PASID) to locate a PASID-entry. The context entry is to include at least one of a page-table pointer to a page-table translation structure and a PASID. The PASID-entry is to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second-level translation structure. The PASID is to be supplied by the device. At least one of the apparatus, the context entry, and the PASID entry is to include one or more control fields to indicate whether the first-level page-table pointer or the second-level page-table pointer is to be used.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 11, 2023
    Assignee: Intel Corporation
    Inventors: Utkarsh Y. Kakaiya, Sanjay Kumar, Rajesh M. Sankaran, Philip R. Lantz, Ashok Raj, Kun Tian
  • Patent number: 11656899
    Abstract: Implementations of the disclosure provide a processing device comprising an address translation circuit to intercept a work request from an I/O device. The work request comprises a first ASID to map to a work queue. A second ASID of a host is allocated for the first ASID based on the work queue. The second ASID is allocated to at least one of: an ASID register for a dedicated work queue (DWQ) or an ASID translation table for a shared work queue (SWQ). Responsive to receiving a work submission from the SVM client to the I/O device, the first ASID of the application container is translated to the second ASID of the host machine for submission to the I/O device using at least one of: the ASID register for the DWQ or the ASID translation table for the SWQ based on the work queue associated with the I/O device.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: May 23, 2023
    Assignee: Intel Corporation
    Inventors: Sanjay Kumar, Rajesh M. Sankaran, Gilbert Neiger, Philip R. Lantz, Jason W. Brandt, Vedvyas Shanbhogue, Utkarsh Y. Kakaiya, Kun Tian