Patents by Inventor Kun Tian
Kun Tian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11921632Abstract: Various embodiments are generally directed to virtualized systems. A first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (VM) on the processor, the first guest memory page corresponding to a first byte-addressable memory. The execution of the VM and the application on the processor may be paused. The first guest memory page may be migrated to a target memory page in a second byte-addressable memory, the target memory page comprising one of a target host memory page and a target guest memory page, the second byte-addressable memory having an access speed faster than an access speed of the first byte-addressable memory.Type: GrantFiled: March 15, 2022Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Yao Zu Dong, Kun Tian, Fengguang Wu, Jingqi Liu
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Publication number: 20240012735Abstract: In an embodiment, a processor for redirecting requests includes a processing engine to execute a guest system, and monitoring circuitry coupled to the processing engine. The monitoring circuitry may be to: receive, from the guest system, a first request to access a first virtual counter; in response to a receipt of the first request, determine, based a mapping register of the processor, a first physical counter mapped to the first virtual counter; and redirect the first request to the first physical counter mapped to the first virtual counter. Other embodiments are described and claimed.Type: ApplicationFiled: December 24, 2020Publication date: January 11, 2024Inventors: Wei Wang, Matthew Merten, Beeman Strong, Andreas Kleen, Kan Liang, Gilbert Neiger, Kun Tian, Like Xu
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Publication number: 20230418762Abstract: Embodiments of apparatuses, methods, and systems for unified address translation for virtualization of input/output devices are described. In an embodiment, an apparatus includes first circuitry to use at least an identifier of a device to locate a context entry and second circuitry to use at least a process address space identifier (PASID) to locate a PASID-entry. The context entry is to include at least one of a page-table pointer to a page-table translation structure and a PASID. The PASID-entry is to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second-level translation structure. The PASID is to be supplied by the device. At least one of the apparatus, the context entry, and the PASID entry is to include one or more control fields to indicate whether the first-level page-table pointer or the second-level page-table pointer is to be used.Type: ApplicationFiled: May 22, 2023Publication date: December 28, 2023Applicant: Intel CorporationInventors: Utkarsh Y. Kakaiya, Sanjay Kumar, Rajesh M. Sankaran, Philip R. Lantz, Ashok Raj, Kun Tian
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Patent number: 11768781Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.Type: GrantFiled: May 27, 2022Date of Patent: September 26, 2023Assignee: Intel CorporationInventors: Niranjan L. Cooray, Abhishek R. Appu, Altug Koker, Joydeep Ray, Balaji Vembu, Pattabhiraman K, David Puffer, David J. Cowperthwaite, Rajesh M. Sankaran, Satyeshwar Singh, Sameer Kp, Ankur N. Shah, Kun Tian
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Patent number: 11734209Abstract: Implementations of the disclosure provide processing device comprising: an interrupt managing circuit to receive an interrupt message directed to an application container from an assignable interface (AI) of an input/output (I/O) device. The interrupt message comprises an address space identifier (ASID), an interrupt handle and a flag to distinguish the interrupt message from a direct memory access (DMA) message. Responsive to receiving the interrupt message, a data structure associated with the interrupt managing circuit is identified. An interrupt entry from the data structure is selected based on the interrupt handle. It is determined that the ASID associated with the interrupt message matches an ASID in the interrupt entry. Thereupon, an interrupt in the interrupt entry is forwarded to the application container.Type: GrantFiled: December 14, 2021Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Sanjay Kumar, Rajesh M. Sankaran, Philip R. Lantz, Utkarsh Y. Kakaiya, Kun Tian
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Publication number: 20230259884Abstract: Described herein is a technique for deriving and using a member profile-to-job posting graph that includes a plurality of implicit facets that map member profiles to job postings. Each implicit facet is a combination of member profile attributes linked with job profile attributes, such that a member profile is linked to the implicit facet when the member profile has member profile attribute values that match those of the implicit facet, and a job posting is linked to the implicit facet when the job posting has job attribute values that match those of the implicit facet. Using the graph, information about the potential applicant pool for a new job posting can be derived and presented to the person who is creating the new job posting.Type: ApplicationFiled: February 17, 2022Publication date: August 17, 2023Inventors: Wen Pu, Yuchin Juan, Ping Liu, Kun Tian, Dawei Wang
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Publication number: 20230251912Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Applicant: Intel CorporationInventors: Utkarsh Y. KAKAIYA, Rajesh SANKARAN, Sanjay KUMAR, Kun TIAN, Philip LANTZ
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Patent number: 11715174Abstract: Embodiments described herein provide techniques enable a graphics processor to continue processing operations during the reset of a compute unit that has experienced a hardware fault. Threads and associated context state for a faulted compute unit can be migrated to another compute unit of the graphics processor and the faulting compute unit can be reset while processing operations continue.Type: GrantFiled: March 3, 2022Date of Patent: August 1, 2023Assignee: Intel CorporationInventors: Murali Ramadoss, Balaji Vembu, Eric C. Samson, Kun Tian, David J. Cowperthwaite, Altug Koker, Zhi Wang, Joydeep Ray, Subramaniam M. Maiyuran, Abhishek R. Appu
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Patent number: 11698866Abstract: Embodiments of apparatuses, methods, and systems for unified address translation for virtualization of input/output devices are described. In an embodiment, an apparatus includes first circuitry to use at least an identifier of a device to locate a context entry and second circuitry to use at least a process address space identifier (PASID) to locate a PASID-entry. The context entry is to include at least one of a page-table pointer to a page-table translation structure and a PASID. The PASID-entry is to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second-level translation structure. The PASID is to be supplied by the device. At least one of the apparatus, the context entry, and the PASID entry is to include one or more control fields to indicate whether the first-level page-table pointer or the second-level page-table pointer is to be used.Type: GrantFiled: December 29, 2017Date of Patent: July 11, 2023Assignee: Intel CorporationInventors: Utkarsh Y. Kakaiya, Sanjay Kumar, Rajesh M. Sankaran, Philip R. Lantz, Ashok Raj, Kun Tian
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Patent number: 11656916Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.Type: GrantFiled: June 29, 2021Date of Patent: May 23, 2023Assignee: Intel CorporationInventors: Utkarsh Y. Kakaiya, Rajesh Sankaran, Sanjay Kumar, Kun Tian, Philip Lantz
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Patent number: 11656899Abstract: Implementations of the disclosure provide a processing device comprising an address translation circuit to intercept a work request from an I/O device. The work request comprises a first ASID to map to a work queue. A second ASID of a host is allocated for the first ASID based on the work queue. The second ASID is allocated to at least one of: an ASID register for a dedicated work queue (DWQ) or an ASID translation table for a shared work queue (SWQ). Responsive to receiving a work submission from the SVM client to the I/O device, the first ASID of the application container is translated to the second ASID of the host machine for submission to the I/O device using at least one of: the ASID register for the DWQ or the ASID translation table for the SWQ based on the work queue associated with the I/O device.Type: GrantFiled: August 17, 2021Date of Patent: May 23, 2023Assignee: Intel CorporationInventors: Sanjay Kumar, Rajesh M. Sankaran, Gilbert Neiger, Philip R. Lantz, Jason W. Brandt, Vedvyas Shanbhogue, Utkarsh Y. Kakaiya, Kun Tian
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Publication number: 20230153143Abstract: Creating hybrid virtual devices using a plurality of physical functions. A processor of a device may identify a plurality of physical functions accessible to the device, the plurality of physical functions including a first physical function and a second physical function. The processor may create a virtual device to comprise the first physical function to provide a first capability and the second physical function to provide a second capability, wherein the first capability and second capability are different capabilities.Type: ApplicationFiled: January 17, 2023Publication date: May 18, 2023Applicant: Intel CorporationInventors: SHAOPENG HE, ANJALI SINGHAI JAIN, UTKARSH Y. KAKAIYA, YADONG LI, ELIEL LOUZOUN, KUN TIAN, BRADLEY BURRES, RORY HARRIS, YAN ZHAO
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Publication number: 20230108461Abstract: Examples described herein relate to circuitry configured to generate at least one virtual device interface to utilize the processor circuitry and provide the at least one virtual device interface to a server to assign to a process to provide the process with capability to utilize the processor circuitry. In some examples, the processor circuitry is to perform one or more of local area network access, cryptographic processing, and/or storage access. In some examples, the storage access comprises access to one or more Non-volatile Memory Express (NVMe) devices.Type: ApplicationFiled: November 30, 2022Publication date: April 6, 2023Inventors: Shaopeng HE, Anjali Singhai JAIN, Yadong LI, Eliel LOUZOUN, Bradley A. BURRES, Utkarsh Y. KAKAIYA, Kun TIAN, Baolu LU, Yan ZHAO, Madhusudan CHITTIM MUNIRATHNAM, Lingyu LIU
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Patent number: 11573870Abstract: Examples may include a computing platform having a host driver to get a packet descriptor of a received packet stored in a receive queue and to modify the packet descriptor from a first format to a second format. The computing platform also includes a guest virtual machine including a guest driver coupled to the host driver, the guest driver to receive the modified packet descriptor and to read a packet buffer stored in the receive queue using the modified packet descriptor, the packet buffer corresponding to the packet descriptor.Type: GrantFiled: December 6, 2018Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Manasi Deval, Nrupal Jani, Anjali Singhai Jain, Parthasarathy Sarangam, Mitu Aggarwal, Neerav Parikh, Kiran Patil, Rajesh M. Sankaran, Sanjay K. Kumar, Utkarsh Y. Kakaiya, Philip Lantz, Kun Tian
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Patent number: 11556437Abstract: Examples include a method of live migrating a virtual device by creating a virtual device in a virtual machine, creating first and second interfaces for the virtual device, transferring data over the first interface, detecting a disconnection of the virtual device from the virtual machine, switching data transfers for the virtual device from the first interface to the second interface, detecting a reconnection of the virtual device to the virtual machine, and switching data transfers for the virtual device from the second interface to the first interface.Type: GrantFiled: December 6, 2018Date of Patent: January 17, 2023Assignee: Intel CorporationInventors: Mitu Aggarwal, Nrupal Jani, Manasi Deval, Kiran Patil, Parthasarathy Sarangam, Rajesh M. Sankaran, Sanjay K. Kumar, Utkarsh Y. Kakaiya, Philip Lantz, Kun Tian
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Patent number: 11556436Abstract: Examples may include a method of protecting memory and I/O transactions. The method includes allocating memory for an application, assigning a resource of a physical device to the application, assigning a process address space identifier to the assigned resource, creating a security enclave to protect the allocated memory of the application, and associating the security enclave with the process address space identifier to protect the allocated memory and the assigned resource.Type: GrantFiled: December 6, 2018Date of Patent: January 17, 2023Assignee: Intel CorporationInventors: Manasi Deval, Nrupal Jani, Parthasarathy Sarangam, Mitu Aggarwal, Kiran Patil, Rajesh M. Sankaran, Sanjay K. Kumar, Utkarsh Y. Kakaiya, Philip Lantz, Kun Tian
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Patent number: 11556363Abstract: Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.Type: GrantFiled: March 31, 2017Date of Patent: January 17, 2023Assignee: INTEL CORPORATIONInventors: Sanjay Kumar, Philip R. Lantz, Kun Tian, Utkarsh Y. Kakaiya, Rajesh M. Sankaran
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Patent number: 11551400Abstract: A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.Type: GrantFiled: October 16, 2020Date of Patent: January 10, 2023Assignee: INTEL CORPORATIONInventors: Prasoonkumar Surti, Tomas G. Akenine-Moller, David J. Cowperthwaite, Kun Tian, Peter L. Doyle, Brent E. Insko, Adam T. Lake
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Patent number: 11513924Abstract: Examples may include a method of instantiating a virtual machine; instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device by receiving input data requesting assigned resources for the virtual device, allocating assigned resources to the virtual device based at least in part on the input data, and mapping a page location in an address space of the shared physical device for a selected one of the assigned resources to a page location in a memory-mapped input/output (MMIO) space of the virtual device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the MMIO space of the virtual device.Type: GrantFiled: December 6, 2018Date of Patent: November 29, 2022Assignee: Intel CorporationInventors: Nrupal Jani, Manasi Deval, Anjali Singhai Jain, Parthasarathy Sarangam, Mitu Aggarwal, Neerav Parikh, Alexander H. Duyck, Kiran Patil, Rajesh M. Sankaran, Sanjay K. Kumar, Utkarsh Y. Kakaiya, Philip Lantz, Kun Tian
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Patent number: 11504730Abstract: Disclosed is a method for calculating instantaneous sprinkler strength comprising: ensuring that a translational sprinkler (1) maintains a stable operating state, placing b rain barrels (3) at a distance of a metres from the translational sprinkler (1), and moving the translational sprinkler (1) to obtain measurement data; calculating movement time, and the average sprayed water depth received by the rain barrels (3); assuming the distribution form of the amount of water of the translational sprinkler (1), establishing a function relationship between an instantaneous sprinkler strength ht and the movement time t, and calculating a variable in the function relationship; and substituting into the established function relationship a specific numerical value of an instantaneous point in time t of the movement of the translational sprinkler (1), so that the value of ht obtained is a numerical value of the instantaneous sprinkler strength of the translational sprinkler (1).Type: GrantFiled: November 22, 2016Date of Patent: November 22, 2022Assignee: Jiangsu UniversityInventors: Xingye Zhu, Junping Liu, Shouqi Yuan, Kun Tian, Jinghong Wan