Patents by Inventor Kun Tian

Kun Tian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190391937
    Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 26, 2019
    Inventors: NIRANJAN L. COORAY, ABHISHEK R. APPU, ALTUG KOKER, JOYDEEP RAY, BALAJI VEMBU, PATTABHIRAMAN K, DAVID PUFFER, DAVID J. COWPERTHWAITE, RAJESH M. SANKARAN, SATYESHWAR SINGH, SAMEER KP, ANKUR N. SHAH, KUN TIAN
  • Publication number: 20190378238
    Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for a graphics processor comprising a compute unit to execute multiple concurrent threads and a memory coupled with and on a same package as the compute unit. The memory can store thread state for a suspended thread and the compute unit can detect that multiple concurrent threads of the compute unit are blocked from execution. Upon detection, the compute unit can select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and select an additional thread to be executed. The compute unit can then replace the victim thread with an additional thread to be executed. The additional thread to be executed can be based on a blocking event for the additional thread.
    Type: Application
    Filed: August 20, 2019
    Publication date: December 12, 2019
    Applicant: Intel Corporation
    Inventors: Murali Ramadoss, Balaji Vembu, Eric C. Samson, Kun Tian, David J. Cowperthwaite, Altug Koker, Zhi Wang, Joydeep Ray, Subramaniam M. Maiyuran, Abhishek R. Appu
  • Publication number: 20190370050
    Abstract: A processing device comprises an address translation circuit to intercept a work request from an I/O device. The work request comprises a first ASID to map to a work queue. A second ASID of a host is allocated for the first ASID based on the work queue. The second ASID is allocated to at least one of: an ASID register for a dedicated work queue (DWQ) or an ASID translation table for a shared work queue (SWQ). Responsive to receiving a work submission from the SVM client to the I/O device, the first ASID of the application container is translated to the second ASID of the host machine for submission to the I/O device using at least one of: the ASID register for the DWQ or the ASID translation table for the SWQ based on the work queue associated with the I/O device.
    Type: Application
    Filed: February 22, 2017
    Publication date: December 5, 2019
    Inventors: Sanjay KUMAR, Rajesh M. SANKARAN, Gilbert NEIGER, Philip R. LANTZ, Jason W. BRANDT, Vedvyas SHANBHOGUE, Utkarsh Y. KAKAIYA, Kun TIAN
  • Publication number: 20190361728
    Abstract: Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.
    Type: Application
    Filed: March 31, 2017
    Publication date: November 28, 2019
    Applicant: INTEL CORPORATION
    Inventors: SANJAY KUMAR, PHILIP R. LANTZ, KUN TIAN, UTKARSH Y. KAKAIYA, RAJESH M. SANKARAN
  • Patent number: 10482567
    Abstract: An apparatus and method are described for intelligent resource provisioning for shadow structures. For example, one embodiment of an apparatus comprises: graphics processing unit (GPU) to process graphics commands and responsively render a plurality of image frames in a graphics memory address space; shadow structure management logic to reserve one or more shadow slots in the graphics memory address space in which to store shadow instances of different GPU contexts; and the shadow structure management logic to implement a partial shadowing policy for shadowing GPU contexts in the shadow slots, the partial shadowing policy based on characteristics of pages of the GPU contexts.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Zhiyuan Lv, Kun Tian
  • Patent number: 10474489
    Abstract: Examples may include techniques to run one or more containers on a virtual machine (VM). Examples include cloning a first VM to result in a second VM. The cloned first VM may run at least a set of containers capable of separately executing one or more applications. In some examples, some cloned containers are stopped at either the first or second VMs to allow for at least some resources provisioned to support the first or second VMs to be reused or recycled at a hosting node. In other examples, the second VM is migrated from the hosting node to a destination hosting node to further enable resources to be reused or recycled at the hosting node.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: November 12, 2019
    Assignee: INTEL CORPORATION
    Inventors: Yao Zu Dong, Kun Tian
  • Patent number: 10467048
    Abstract: Examples may include techniques for virtual machine (VM) migration. Examples may include selecting a VM for live migration from a source node to a destination node, predicting a time period associated with the live migration, and selecting another VM from which allocated source node bandwidth may borrowed to facilitate the live migration within the predicted time.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: November 5, 2019
    Assignee: INTEL CORPORATION
    Inventors: Yao Zu Dong, Kun Tian
  • Patent number: 10467033
    Abstract: Embodiments of the invention enable dynamic level boosting of operations across virtualization layers to enable efficient nested virtualization. Embodiments of the invention execute a first virtual machine monitor (VMM) to virtualize system hardware. A nested virtualization environment is created by executing a plurality of upper level VMMs via virtual machines (VMs). These upper level VMMs are used to execute an upper level virtualization layer including an operating system (OS). During operation of the above described nested virtualization environment, a privileged instruction issued from an OS is trapped and emulated via the respective upper level VMM (i.e., the VMM that creates the VM for that OS). Embodiments of the invention enable the emulation of the privileged instruction via a lower level VMM. In some embodiments, the emulated instruction is executed via the first VMM with little to no involvement of any intermediate virtualization layers residing between the first and upper level VMMs.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: November 5, 2019
    Assignee: INTEL CORPORATION
    Inventors: Kun Tian, Yao Zu Dong
  • Patent number: 10460417
    Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for an apparatus comprising a thread dispatcher to dispatch a thread for execution; a compute unit having a single instruction, multiple thread architecture, the compute unit to execute multiple concurrent threads; and a memory coupled with the compute unit, the memory to store thread state for a suspended thread, wherein the compute unit is to: detect that all threads on the compute unit are blocked from execution, select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and replace the victim thread with an additional thread to be executed.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Murali Ramadoss, Balaji Vembu, Eric C. Samson, Kun Tian, David J. Cowperthwaite, Altug Koker, Zhi Wang, Joydeep Ray, Subramaniam M. Maiyuran, Abhishek R. Appu
  • Patent number: 10452495
    Abstract: It includes techniques to provide for reliable primary and secondary containers arranged to separately execute an application that receives request packets for processing by the application. The request packets may be received from a client coupled with a server arranged to host the primary container or the secondary container. The client coupled with the server through a network. Coarse-grained lock-stepping (COLO) methods may be utilized to facilitate in providing the reliable primary and secondary containers.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: October 22, 2019
    Assignee: INTEL CORPORATION
    Inventors: Yao Zu Dong, Yunhong Jiang, Kun Tian
  • Publication number: 20190295210
    Abstract: A display engine comprises a surface splitter to generate frame buffer coordinates to split frame buffer data into a plurality of regions, each corresponding to a frame buffer coordinate, a pipeline, including a plurality of pipes, to receive the frame buffer coordinates, wherein two or more of the plurality of pipes operate in parallel to process frame buffer data corresponding to a region of the frame buffer identified by the frame buffer coordinates, a first of a plurality of transcoders to merge the frame buffer data from each of the two or more pipes into an output signal whenever the display engine is operating in a multi-pipe collaboration mode and a multiplexer (Mux) and multi-stream arbiter to control an order of transmission of the frame buffer data from each of the two or more pipes to the first transcoder based on a fetch order received from the surface splitter.
    Type: Application
    Filed: July 2, 2016
    Publication date: September 26, 2019
    Inventors: Dinyu PEI, Kun TIAN
  • Publication number: 20190286479
    Abstract: Technologies for scheduling workload submissions for a graphics processing unit (GPU) in a virtualization environment include a GPU scheduler embodied in a computing device. The virtualization environment includes a number of different virtual machines that are configured with a native graphics driver. The GPU scheduler receives GPU commands from the different virtual machines, dynamically selects a scheduling policy, and schedules the GPU commands for processing by the GPU.
    Type: Application
    Filed: October 10, 2018
    Publication date: September 19, 2019
    Inventors: Kun Tian, Zhiyuan Lv, Yao Zu Dong
  • Publication number: 20190269077
    Abstract: Disclosed is a method for calculating the depth of sprayed water of a translational sprinkler in different working conditions, involving placing rain barrels (3) in n rows in the movement direction of a translational sprinkler (1), each row having m barrels, such that the spray radius of rain droplets can completely cover the rain barrels (3) while ensuring that the translational sprinkler (1) is spraying stably; calculating the average sprinkler strength of each rain barrel (3); drawing a relationship curve of the sprinkler strength and the distance from the centre; setting the movement speed s of the translational sprinkler (1); establishing a function relationship between a sprinkler strength d? and time t; calculating the time t2 needed for the translational sprinkler (1) to completely pass one of the rain barrels (3); and with the condition that the movement time is t2, performing mathematical integration on the sprinkler strength function to obtain the sprinkled depth of water at a certain rain barrel (
    Type: Application
    Filed: November 22, 2016
    Publication date: September 5, 2019
    Inventors: Xingye ZHU, Shouqi YUAN, Junping LIU, Jinghong WAN, Kun TIAN
  • Patent number: 10380039
    Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Niranjan L. Cooray, Satyeshwar Singh, Sameer KP, Ankur N. Shah, Kun Tian, Abhishek R. Appu, Altug Koker, Joydeep Ray, Balaji Vembu, Pattabhiraman K, David Puffer, David J. Cowperthwaite, Rajesh M. Sankaran
  • Patent number: 10375905
    Abstract: A detachable frame of a light-small sprinkling machine includes angle steel pieces, tiepieces, support bars, support upright rods, top rod with slots, and wheels. The components of the frame are connected through threaded connections, so that the frame can be disassembled and removed easily. The distance between sprinkler heads and the mounting height of the sprinkler heads may be changed by means of free movement of turning hooks in the top rod with slots. The number of spans of the rod of the machine are be selected according to the topographic structure and can be changed by means of threaded holes in the two ends of the top rod with slots, and thereby the length of the rod can be changed. Employing low-pressure sprinkler heads and utilizing the turning effect of movable swivel shafts, the irrigation sprinkling machine can be turned to any direction freely.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: August 13, 2019
    Assignee: Jiangsu University
    Inventors: Xingye Zhu, Shouqi Yuan, Junping Liu, Kun Tian, Jinghong Wan, Ya Bao, Xingfa Liu
  • Patent number: 10375022
    Abstract: An apparatus, system, method, and machine-readable medium are disclosed. In one embodiment the apparatus is a network interface controller that includes one virtual function owned by a virtual machine present in the computer system. The controller includes a simple filtering agent that is associated with the first virtual function. The agent enforces simple filter rules for received network packets. The simple filter rules are capable of blocking the network packets from reaching the virtual machine. The apparatus also includes another virtual function that is owned by a virtual machine monitor present in the computer system. The controller also includes a side bounce filtering agent to forward the first network packet to the second virtual function if the first packet is blocked by the at least one of the one or more simple filter rules.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Yaozu Dong, Kun Tian
  • Patent number: 10365126
    Abstract: A distributed optical fiber disturbance positioning system based on the asymmetric dual Mach-Zehnder interference, unlike traditional dual Mach-Zehnder distributed optical fiber disturbance sensing system, the present invention adopts two narrow-bandwidth optical sources (1a, 1b) and adopts corresponding DWDM (3a, 3b) before the detector (4a, 4b) to filter the backscatter noise of the optical fiber, and can solve the problems of having too low SNR due to backscatter influence when the sensing distance is long. The present invention also provides a positioning method for applying the system, which obtains the TFD of the disturbance frame signals by using the time-frequency analysis method based on the short-term average frequency, and takes the points near the point of maximum frequency as the effective signal segment for performing cross-correlation time delay estimation, thus obtaining the delay, and the disturbance position.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: July 30, 2019
    Assignee: Tianjin University
    Inventors: Kun Liu, Tiegen Liu, Junfeng Jiang, Chunyu Ma, Tianjiao Chai, Chang He, Miao Tian, Zhichen Li
  • Publication number: 20190220301
    Abstract: An apparatus and method are described for implementing a hybrid layer of address mapping for an IOMMU implementation.
    Type: Application
    Filed: September 26, 2016
    Publication date: July 18, 2019
    Inventors: Xiao ZHENG, Yao Zu DONG, Kun TIAN
  • Patent number: 10355030
    Abstract: A display panel and a display apparatus are provided. The display panel includes: a substrate; multiple first-layer wires disposed on the substrate; and an insulating dielectric layer disposed on the first-layer wires. A dielectric constant of the insulating dielectric layer is higher than dielectric constants of silicon oxide layer and silicon nitride layer. The insulating dielectric layer includes a composition. The composition includes a first component and a second component. A dielectric constant of the first component is lower than the dielectric constants of silicon oxide layer and silicon nitride layer. A dielectric constant of the second component is higher than the dielectric constants of silicon oxide layer and silicon nitride layer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 16, 2019
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: En-Tsung Cho, Kun Fan, Yiqun Tian
  • Patent number: D850367
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: June 4, 2019
    Assignee: BAIDU ONLINE NETWORK TECHNOLOGY (BEIJING) CO., LTD.
    Inventors: Tao Xiong, Zhe Wang, Xiaodong Li, Yuan Tian, Xingfei Ge, Kun Jing, Kaihua Zhu