Patents by Inventor Kun-Tsang Chuang

Kun-Tsang Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10790391
    Abstract: The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Hsin-Chi Chen, Kun-Tsang Chuang
  • Publication number: 20200295046
    Abstract: Bulk semiconductor substrates configured to exhibit semiconductor-on-insulator (SOI) behavior, and corresponding methods of fabrication, are disclosed herein. An exemplary bulk substrate configured to exhibit SOI behavior includes a first isolation trench that defines a channel region of the bulk substrate and a second isolation trench that defines an active region that includes the channel region. The first isolation trench includes a first isolation trench portion and a second isolation trench portion disposed over the first isolation trench portion. A first isolation material fills the first isolation trench portion, and an epitaxial material fills the second isolation trench portion. The epitaxial material is disposed on the first isolation material. A second isolation material fills the second isolation trench. A portion of the bulk substrate underlying the first isolation trench and the channel region is configured to have a higher resistance than the bulk substrate.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Gulbagh Singh, Kun-Tsang Chuang, Hsin-Chi Chen
  • Publication number: 20200251554
    Abstract: The present disclosure describes a fabrication method that prevents divots during the formation of isolation regions in integrated circuit fabrication. In some embodiments, the method of forming the isolation regions includes depositing a protective layer over a semiconductor layer; patterning the protective layer to expose areas of the semiconductor layer; depositing an oxide on the exposed areas the semiconductor layer and between portions of the patterned protective layer; etching a portion of the patterned protective layer to expose the semiconductor layer; etching the exposed semiconductor layer to form isolation openings in the semiconductor layer; and filling the isolation openings with a dielectric to form the isolation regions.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh SINGH, Hsin-Chi CHEN, Kun-Tsang CHUANG
  • Patent number: 10672777
    Abstract: A method for manufacturing a semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively formed on the silicon substrate and connected to each other. A limiting block is formed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer is formed to blanketly cover the first structure, the second structure and the limiting block, in which the BARC layer includes a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are formed on the external surface of the BARC layer.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Wei Su, Yung-Lung Hsu, Chih-Hsun Lin, Kun-Tsang Chuang, Chiang-Ming Chuang, Chia-Yi Tseng
  • Patent number: 10672795
    Abstract: Bulk semiconductor substrates configured to exhibit semiconductor-on-insulator (SOI) behavior, and corresponding methods of fabrication, are disclosed herein. An exemplary bulk substrate configured to exhibit SOI behavior includes a first isolation trench that defines a channel region of the bulk substrate and a second isolation trench that defines an active region that includes the channel region. The first isolation trench includes a first isolation trench portion and a second isolation trench portion disposed over the first isolation trench portion. A first isolation material fills the first isolation trench portion, and an epitaxial material fills the second isolation trench portion. The epitaxial material is disposed on the first isolation material. A second isolation material fills the second isolation trench. A portion of the bulk substrate underlying the first isolation trench and the channel region is configured to have a higher resistance than the bulk substrate.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gulbagh Singh, Kun-Tsang Chuang, Hsin-Chi Chen
  • Publication number: 20200152648
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
  • Publication number: 20200135875
    Abstract: The present disclosure relates to a semiconductor structure includes a substrate with a top surface and first and second devices formed on the top surface of the substrate. The semiconductor structure also includes a deep isolation structure formed in the substrate and between the first and second devices. The deep isolation structure includes a top portion formed at the top surface and having a top width and a bottom surface having a bottom width larger than the top width.
    Type: Application
    Filed: December 30, 2019
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh SINGH, Tsung-Han TSAI, Kun-Tsang CHUANG
  • Patent number: 10636695
    Abstract: Negatively sloped isolation structures are formed on a semiconductor substrate to isolate devices from one another. The negatively sloped isolation structures have a top critical dimension which is smaller than a bottom critical dimension. The negatively sloped isolation structures may penetrate through an insulator layer of a silicon-on-insulator structure arrangement.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gulbagh Singh, Tsung-Han Tsai, Kun-Tsang Chuang
  • Patent number: 10636870
    Abstract: The present disclosure describes a fabrication method that prevents divots during the formation of isolation regions in integrated circuit fabrication. In some embodiments, the method of forming the isolation regions includes depositing a protective layer over a semiconductor layer; patterning the protective layer to expose areas of the semiconductor layer; depositing an oxide on the exposed areas the semiconductor layer and between portions of the patterned protective layer; etching a portion of the patterned protective layer to expose the semiconductor layer; etching the exposed semiconductor layer to form isolation openings in the semiconductor layer; and filling the isolation openings with a dielectric to form the isolation regions.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Hsin-Chi Chen, Kun-Tsang Chuang
  • Publication number: 20200058736
    Abstract: The present disclosure describes a fabrication method that prevents divots during the formation of isolation regions in integrated circuit fabrication. In some embodiments, the method of forming the isolation regions includes depositing a protective layer over a semiconductor layer; patterning the protective layer to expose areas of the semiconductor layer; depositing an oxide on the exposed areas the semiconductor layer and between portions of the patterned protective layer; etching a portion of the patterned protective layer to expose the semiconductor layer; etching the exposed semiconductor layer to form isolation openings in the semiconductor layer; and filling the isolation openings with a dielectric to form the isolation regions.
    Type: Application
    Filed: August 15, 2018
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Hsin-Chi Chen, Kun-Tsang Chuang
  • Publication number: 20200051851
    Abstract: The present disclosure describes a fabrication method that can form air-gaps in shallow trench isolation structures (STI) structures. For example, the method includes patterning a semiconductor layer over a substrate to form semiconductor islands and oxidizing the sidewall surfaces of the semiconductor islands to form first liners on the sidewall surfaces. Further, the method includes depositing a second liner over the first liners and the substrate and depositing a first dielectric layer between the semiconductor islands. The second liner between the first dielectric layer and the first liners is removed to form openings between the first dielectric layer and the first liners. A second dielectric layer is deposited over the first dielectric layer to enclose the openings and form air-gaps between the first dielectric layer and the first liners so that the gaps are positioned along the first liners.
    Type: Application
    Filed: October 18, 2019
    Publication date: February 13, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh SINGH, Hsin-Chi Chen, Kun-Tsang Chuang
  • Patent number: 10546937
    Abstract: The present disclosure relates to a semiconductor structure includes a substrate with a top surface and first and second devices formed on the top surface of the substrate. The semiconductor structure also includes a deep isolation structure formed in the substrate and between the first and second devices. The deep isolation structure includes a top portion formed at the top surface and having a top width and a bottom surface having a bottom width larger than the top width.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: January 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Tsung-Han Tsai, Kun-Tsang Chuang
  • Patent number: 10535670
    Abstract: A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
  • Publication number: 20200006386
    Abstract: Bulk semiconductor substrates configured to exhibit semiconductor-on-insulator (SOI) behavior, and corresponding methods of fabrication, are disclosed herein. An exemplary bulk substrate configured to exhibit SOI behavior includes a first isolation trench that defines a channel region of the bulk substrate and a second isolation trench that defines an active region that includes the channel region. The first isolation trench includes a first isolation trench portion and a second isolation trench portion disposed over the first isolation trench portion. A first isolation material fills the first isolation trench portion, and an epitaxial material fills the second isolation trench portion. The epitaxial material is disposed on the first isolation material. A second isolation material fills the second isolation trench. A portion of the bulk substrate underlying the first isolation trench and the channel region is configured to have a higher resistance than the bulk substrate.
    Type: Application
    Filed: August 30, 2018
    Publication date: January 2, 2020
    Inventors: Gulbagh Singh, Kun-Tsang Chuang, Hsin-Chi Chen
  • Publication number: 20200006560
    Abstract: The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.
    Type: Application
    Filed: August 30, 2018
    Publication date: January 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh SINGH, Hsin-Chi CHEN, Kun-Tsang CHUANG
  • Publication number: 20200006114
    Abstract: Negatively sloped isolation structures are formed on a semiconductor substrate to isolate devices from one another. The negatively sloped isolation structures have a top critical dimension which is smaller than a bottom critical dimension. The negatively sloped isolation structures may penetrate through an insulator layer of a silicon-on-insulator structure arrangement.
    Type: Application
    Filed: September 11, 2019
    Publication date: January 2, 2020
    Inventors: Gulbagh Singh, Tsung-Han Tsai, Kun-Tsang Chuang
  • Patent number: 10522390
    Abstract: The present disclosure describes a fabrication method that can form air-gaps in shallow trench isolation structures (STI) structures. For example, the method includes patterning a semiconductor layer over a substrate to form semiconductor islands and oxidizing the sidewall surfaces of the semiconductor islands to form first liners on the sidewall surfaces. Further, the method includes depositing a second liner over the first liners and the substrate and depositing a first dielectric layer between the semiconductor islands. The second liner between the first dielectric layer and the first liners is removed to form openings between the first dielectric layer and the first liners. A second dielectric layer is deposited over the first dielectric layer to enclose the openings and form air-gaps between the first dielectric layer and the first liners so that the gaps are positioned along the first liners.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Hsin-Chi Chen, Kun-Tsang Chuang
  • Publication number: 20190393078
    Abstract: The present disclosure describes a fabrication method that can form air-gaps in shallow trench isolation structures (STI) structures. For example, the method includes patterning a semiconductor layer over a substrate to form semiconductor islands and oxidizing the sidewall surfaces of the semiconductor islands to form first liners on the sidewall surfaces. Further, the method includes depositing a second liner over the first liners and the substrate and depositing a first dielectric layer between the semiconductor islands. The second liner between the first dielectric layer and the first liners is removed to form openings between the first dielectric layer and the first liners. A second dielectric layer is deposited over the first dielectric layer to enclose the openings and form air-gaps between the first dielectric layer and the first liners so that the gaps are positioned along the first liners.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh SINGH, Hsin-Chi Chen, Kun-Tsang Chuang
  • Publication number: 20190385892
    Abstract: Negatively sloped isolation structures are formed on a semiconductor substrate to isolate devices from one another. The negatively sloped isolation structures have a top critical dimension which is smaller than a bottom critical dimension. The negatively sloped isolation structures may penetrate through an insulator layer of a silicon-on-insulator structure arrangement.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Inventors: Gulbagh Singh, Tsung-Han Tsai, Kun-Tsang Chuang
  • Publication number: 20190259771
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen