Patents by Inventor Kun-Tsang Chuang

Kun-Tsang Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11211283
    Abstract: Bulk semiconductor substrates configured to exhibit semiconductor-on-insulator (SOI) behavior, and corresponding methods of fabrication, are disclosed herein. An exemplary bulk substrate configured to exhibit SOI behavior includes a first isolation trench that defines a channel region of the bulk substrate and a second isolation trench that defines an active region that includes the channel region. The first isolation trench includes a first isolation trench portion and a second isolation trench portion disposed over the first isolation trench portion. A first isolation material fills the first isolation trench portion, and an epitaxial material fills the second isolation trench portion. The epitaxial material is disposed on the first isolation material. A second isolation material fills the second isolation trench. A portion of the bulk substrate underlying the first isolation trench and the channel region is configured to have a higher resistance than the bulk substrate.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gulbagh Singh, Kun-Tsang Chuang, Hsin-Chi Chen
  • Publication number: 20210375666
    Abstract: Semiconductor-on-insulator (SOI) field effect transistors (FETs) including body regions having different thicknesses may be formed on an SOI substrate by selectively thinning a region of a top semiconductor layer while preventing thinning of an additional region of the top semiconductor layer. An oxidation process or an etch process may be used to thin the region of the top semiconductor layer, and a patterned oxidation barrier mask or an etch mask may be used to prevent oxidation or etching of the additional portion of the top semiconductor layer. Shallow trench isolation structures may be formed prior to, or after, the selective thinning processing steps. FETs having different depletion region configurations may be formed using the multiple thicknesses of the patterned portions of the top semiconductor layer. For example, partially depleted SOI FETs and fully depleted SOI FETs may be provided.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Inventors: Gulbagh Singh, Po-Jen Wang, Kun-Tsang Chuang
  • Patent number: 11183570
    Abstract: The present disclosure relates to a semiconductor structure includes a substrate with a top surface and first and second devices formed on the top surface of the substrate. The semiconductor structure also includes a deep isolation structure formed in the substrate and between the first and second devices. The deep isolation structure includes a top portion formed at the top surface and having a top width and a bottom surface having a bottom width larger than the top width.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Tsung-Han Tsai, Kun-Tsang Chuang
  • Patent number: 11171199
    Abstract: The present disclosure relates to an apparatus that includes a bottom electrode and a dielectric structure. The dielectric structure includes a first dielectric layer on the bottom electrode and the first dielectric layer has a first thickness. The apparatus also includes a blocking layer on the first dielectric layer and a second dielectric layer on the blocking layer. The second dielectric layer has a second thickness that is less than the first thickness. The apparatus further includes a top electrode over the dielectric structure.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ting Chen, Tsung-Han Tsai, Kun-Tsang Chuang, Po-Jen Wang, Ying-Hao Chen, Chien-Cheng Huang
  • Publication number: 20210328009
    Abstract: A semiconductor device includes a substrate, a gate oxide layer formed on the substrate, a gate formed on the gate oxide layer, and a spacer formed adjacent the gate and over the substrate. The spacer includes a void filled with air to prevent leakage of charge to and from the gate, thereby reducing data loss and providing better memory retention. The reduction in charge leakage results from reduced parasitic capacitances, fringing capacitances, and overlap capacitances due to the low dielectric constant of air relative to other spacer materials. The spacer can include multiple layers such as oxide and nitride layers. In some embodiments, the semiconductor device is a multiple-time programmable (MTP) memory device.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 21, 2021
    Inventors: Gulbagh Singh, Kun-Tsang Chuang, Hsin-Chi Chen
  • Publication number: 20210327813
    Abstract: The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.
    Type: Application
    Filed: April 15, 2020
    Publication date: October 21, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gulbagh Singh, Kun-Tsang Chuang, Po-Jen Wang
  • Publication number: 20210328031
    Abstract: The present disclosure relates to a semiconductor structure includes a substrate with a top surface and first and second devices formed on the top surface of the substrate. The semiconductor structure also includes a deep isolation structure formed in the substrate and between the first and second devices. The deep isolation structure includes a top portion formed at the top surface and having a top width and a bottom surface having a bottom width larger than the top width.
    Type: Application
    Filed: December 30, 2019
    Publication date: October 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh SINGH, Tsung-Han TSAI, Kun-Tsang CHUANG
  • Patent number: 11145539
    Abstract: The present disclosure describes a fabrication method that can form air-gaps in shallow trench isolation structures (STI) structures. For example, the method includes patterning a semiconductor layer over a substrate to form semiconductor islands and oxidizing the sidewall surfaces of the semiconductor islands to form first liners on the sidewall surfaces. Further, the method includes depositing a second liner over the first liners and the substrate and depositing a first dielectric layer between the semiconductor islands. The second liner between the first dielectric layer and the first liners is removed to form openings between the first dielectric layer and the first liners. A second dielectric layer is deposited over the first dielectric layer to enclose the openings and form air-gaps between the first dielectric layer and the first liners so that the gaps are positioned along the first liners.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Hsin-Chi Chen, Kun-Tsang Chuang
  • Publication number: 20210305396
    Abstract: A transistor device and method of making the same are disclosed. The transistor device includes one or more air gaps in one or more sidewall spacers. The one or more air gaps may be located adjacent the gate and/or above the source or drain regions of the device. Various embodiments may include different combinations of air gaps formed in one or both sidewall spacers. Various embodiments may include air gaps formed in one or both sidewall spacers adjacent to the gate and/or above the source or drain regions of the device. The formation of the air gaps may reduce unwanted parasitic and/or fringing capacitance.
    Type: Application
    Filed: March 31, 2020
    Publication date: September 30, 2021
    Inventors: Gulbagh Singh, Po-Jen Wang, Kun-Tsang Chuang
  • Patent number: 11121141
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
  • Publication number: 20210210381
    Abstract: A method of making a semiconductor structure includes depositing a first passivation material between adjacent conductive elements on a substrate, wherein a bottommost surface of the first passivation material is coplanar with a bottommost surface of each of the adjacent conductive elements. The method further includes depositing a second passivation material on the substrate, wherein the second passivation material contacts a sidewall of each of the adjacent conductive elements and a sidewall of the first passivation material, a bottommost surface of the second passivation material is coplanar with the bottommost surface of each of the adjacent conductive elements, and the second passivation material is different from the first passivation material.
    Type: Application
    Filed: March 19, 2021
    Publication date: July 8, 2021
    Inventors: Chih-Ming LEE, Hung-Che LIAO, Kun-Tsang CHUANG, Wei-Chung LU
  • Patent number: 10964589
    Abstract: A semiconductor structure includes a substrate, first and second conductors, a passivation material, and a passivation sidewall block. The first and second conductors are on the substrate. The passivation material is between the first and second conductors. The passivation sidewall block is on sidewalls of the first and second conductors and the passivation material.
    Type: Grant
    Filed: August 13, 2017
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Ming Lee, Hung-Che Liao, Kun-Tsang Chuang, Wei-Chung Lu
  • Publication number: 20210057517
    Abstract: The present disclosure relates to an apparatus that includes a bottom electrode and a dielectric structure. The dielectric structure includes a first dielectric layer on the bottom electrode and the first dielectric layer has a first thickness. The apparatus also includes a blocking layer on the first dielectric layer and a second dielectric layer on the blocking layer. The second dielectric layer has a second thickness that is less than the first thickness. The apparatus further includes a top electrode over the dielectric structure.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ting CHEN, Tsung-Han Tsai, Kun-Tsang Chuang, Po-Jen Wang, Ying-Hao Chen, Chien-Cheng Chuang
  • Publication number: 20210043566
    Abstract: A method includes capturing an image of a wafer, the wafer comprising a first conductive contact over an active region of the wafer and a second conductive contact over a shallow trench isolation (STI) region abutting the active region; identifying a brightness of a first contact region in the captured image at which the first conductive contact is rendered; identifying a brightness of a second contact region in the captured image at which the second conductive contact is rendered; and in response to the identified brightness of the first contact region in the captured image being substantially the same as the identified brightness of the second contact region in the captured image, determining that the second conductive contact is shorted to the first conductive contact.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Hsung HO, Chia-Yi TSENG, Chih-Hsun LIN, Kun-Tsang CHUANG, Yung-Lung HSU
  • Publication number: 20210013343
    Abstract: The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 14, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh SINGH, Hsin-Chu CHEN, Kun-Tsang CHUANG
  • Patent number: 10886165
    Abstract: Negatively sloped isolation structures are formed on a semiconductor substrate to isolate devices from one another. The negatively sloped isolation structures have a top critical dimension which is smaller than a bottom critical dimension. The negatively sloped isolation structures may penetrate through an insulator layer of a silicon-on-insulator structure arrangement.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: January 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gulbagh Singh, Tsung-Han Tsai, Kun-Tsang Chuang
  • Publication number: 20200395459
    Abstract: A semiconductor arrangement includes a gate structure disposed between a first source/drain region and a second source/drain region and a first contact disposed over the first source/drain region. The semiconductor arrangement includes a second contact disposed over the second source/drain region and an airgap disposed between the first contact and the second contact and over the gate structure.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Inventors: Gulbagh SINGH, Wang Po-Jen, Kun-Tsang Chuang, Tsung-Han Tsai
  • Patent number: 10818595
    Abstract: A method of fabricating a semiconductor structure includes forming first and second features in a scribe region of a semiconductor substrate in which the first feature has a first electrical resistance, the second feature has a second electrical resistance, and the first electrical resistance is different form the second electrical resistance; forming an interlayer dielectric layer over the first and second features; and forming a first contact in the interlayer dielectric layer and connected to the first feature and a second contact in the interlayer dielectric layer and connected to the second feature.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Hsung Ho, Chia-Yi Tseng, Chih-Hsun Lin, Kun-Tsang Chuang, Yung-Lung Hsu
  • Patent number: 10790391
    Abstract: The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Hsin-Chi Chen, Kun-Tsang Chuang
  • Publication number: 20200295046
    Abstract: Bulk semiconductor substrates configured to exhibit semiconductor-on-insulator (SOI) behavior, and corresponding methods of fabrication, are disclosed herein. An exemplary bulk substrate configured to exhibit SOI behavior includes a first isolation trench that defines a channel region of the bulk substrate and a second isolation trench that defines an active region that includes the channel region. The first isolation trench includes a first isolation trench portion and a second isolation trench portion disposed over the first isolation trench portion. A first isolation material fills the first isolation trench portion, and an epitaxial material fills the second isolation trench portion. The epitaxial material is disposed on the first isolation material. A second isolation material fills the second isolation trench. A portion of the bulk substrate underlying the first isolation trench and the channel region is configured to have a higher resistance than the bulk substrate.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Gulbagh Singh, Kun-Tsang Chuang, Hsin-Chi Chen