Patents by Inventor Kun-Tsang Chuang
Kun-Tsang Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220278042Abstract: The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.Type: ApplicationFiled: May 16, 2022Publication date: September 1, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gulbagh Singh, Kun-Tsang CHUANG, Po-Jen WANG
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Patent number: 11430733Abstract: A method includes capturing an image of a wafer, the wafer comprising a first conductive contact over an active region of the wafer and a second conductive contact over a shallow trench isolation (STI) region abutting the active region; identifying a brightness of a first contact region in the captured image at which the first conductive contact is rendered; identifying a brightness of a second contact region in the captured image at which the second conductive contact is rendered; and in response to the identified brightness of the first contact region in the captured image being substantially the same as the identified brightness of the second contact region in the captured image, determining that the second conductive contact is shorted to the first conductive contact.Type: GrantFiled: October 23, 2020Date of Patent: August 30, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Hsung Ho, Chia-Yi Tseng, Chih-Hsun Lin, Kun-Tsang Chuang, Yung-Lung Hsu
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Publication number: 20220271141Abstract: A transistor device and method of making the same are disclosed. The transistor device includes one or more air gaps in one or more sidewall spacers. The one or more air gaps may be located adjacent the gate and/or above the source or drain regions of the device. Various embodiments may include different combinations of air gaps formed in one or both sidewall spacers. Various embodiments may include air gaps formed in one or both sidewall spacers adjacent to the gate and/or above the source or drain regions of the device. The formation of the air gaps may reduce unwanted parasitic and/or fringing capacitance.Type: ApplicationFiled: May 11, 2022Publication date: August 25, 2022Inventors: Gulbagh Singh, Po-Jen Wang, Kun-Tsang Chuang
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Patent number: 11417749Abstract: A semiconductor arrangement includes a gate structure disposed between a first source/drain region and a second source/drain region and a first contact disposed over the first source/drain region. The semiconductor arrangement includes a second contact disposed over the second source/drain region and an airgap disposed between the first contact and the second contact and over the gate structure.Type: GrantFiled: June 14, 2019Date of Patent: August 16, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Gulbagh Singh, Wang Po-Jen, Kun-Tsang Chuang, Tsung-Han Tsai
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Publication number: 20220246756Abstract: A semiconductor structure includes a substrate assembly and a semiconductor device. The semiconductor device is formed on the substrate assembly, and includes a body region, two active regions, and a butted body. The active regions are disposed at two opposite sides of the body region, and both have a first type conductivity. The body region and the active regions together occupy on a surface region of the substrate assembly. The butted body has a second type conductivity different from the first type conductivity, and is located on the surface region of the substrate assembly so as to permit the body region to be tied to one of the active regions through the butted body.Type: ApplicationFiled: January 29, 2021Publication date: August 4, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Gulbagh SINGH, Kun-Tsang CHUANG
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Patent number: 11404537Abstract: A semiconductor device includes a substrate, a gate oxide layer formed on the substrate, a gate formed on the gate oxide layer, and a spacer formed adjacent the gate and over the substrate. The spacer includes a void filled with air to prevent leakage of charge to and from the gate, thereby reducing data loss and providing better memory retention. The reduction in charge leakage results from reduced parasitic capacitances, fringing capacitances, and overlap capacitances due to the low dielectric constant of air relative to other spacer materials. The spacer can include multiple layers such as oxide and nitride layers. In some embodiments, the semiconductor device is a multiple-time programmable (MTP) memory device.Type: GrantFiled: April 17, 2020Date of Patent: August 2, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Gulbagh Singh, Kun-Tsang Chuang, Hsin-Chi Chen
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Patent number: 11398403Abstract: Semiconductor-on-insulator (SOI) field effect transistors (FETs) including body regions having different thicknesses may be formed on an SOI substrate by selectively thinning a region of a top semiconductor layer while preventing thinning of an additional region of the top semiconductor layer. An oxidation process or an etch process may be used to thin the region of the top semiconductor layer, and a patterned oxidation barrier mask or an etch mask may be used to prevent oxidation or etching of the additional portion of the top semiconductor layer. Shallow trench isolation structures may be formed prior to, or after, the selective thinning processing steps. FETs having different depletion region configurations may be formed using the multiple thicknesses of the patterned portions of the top semiconductor layer. For example, partially depleted SOI FETs and fully depleted SOI FETs may be provided.Type: GrantFiled: May 28, 2020Date of Patent: July 26, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Gulbagh Singh, Po-Jen Wang, Kun-Tsang Chuang
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Publication number: 20220216095Abstract: A semiconductor device may include a source on a first side of a gate. The semiconductor device may include a drain on a second side of the gate, where the second side of the gate is opposite to the first side of the gate. The semiconductor device may include a first contact over the source. The semiconductor device may include a second contact over the drain. The semiconductor device may include an air gap over the gate between at least the first contact and the second contact. The semiconductor device may include at least two dielectric materials in each of a region between the air gap and the first contact and a region between the air gap and the second contact.Type: ApplicationFiled: January 7, 2021Publication date: July 7, 2022Inventors: Gulbagh SINGH, Tsung-Han TSAI, Shih-Lu HSU, Kun-Tsang CHUANG
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Patent number: 11367778Abstract: A transistor device and method of making the same are disclosed. The transistor device includes one or more air gaps in one or more sidewall spacers. The one or more air gaps may be located adjacent the gate and/or above the source or drain regions of the device. Various embodiments may include different combinations of air gaps formed in one or both sidewall spacers. Various embodiments may include air gaps formed in one or both sidewall spacers adjacent to the gate and/or above the source or drain regions of the device. The formation of the air gaps may reduce unwanted parasitic and/or fringing capacitance.Type: GrantFiled: March 31, 2020Date of Patent: June 21, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Gulbagh Singh, Po-Jen Wang, Kun-Tsang Chuang
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Patent number: 11348944Abstract: A circuit includes a base silicon layer, a base oxide layer, a first top silicon layer, a second top silicon layer, a first semiconductor device, and a second semiconductor device. The base oxide layer is formed over the base silicon layer. The first top silicon layer is formed over a first region of the base oxide layer and has a first thickness. The second top silicon layer is formed over a second region of the base oxide layer and has a second thickness less than the first thickness. The first semiconductor device is formed over the first top silicon layer and the second semiconductor device is formed over the second top silicon layer. The ability to fabricate a top silicon layers with differing thicknesses can provide a single substrate having devices with different characteristics, such as having both fully depleted and partially depleted devices on a single substrate.Type: GrantFiled: April 17, 2020Date of Patent: May 31, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Gulbagh Singh, Kuan-Liang Liu, Wang Po-Jen, Kun-Tsang Chuang, Hsin-Chi Chen
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Patent number: 11335638Abstract: The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.Type: GrantFiled: April 15, 2020Date of Patent: May 17, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gulbagh Singh, Kun-Tsang Chuang, Po-Jen Wang
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Patent number: 11264456Abstract: The present disclosure describes a fabrication method that prevents divots during the formation of isolation regions in integrated circuit fabrication. In some embodiments, the method of forming the isolation regions includes depositing a protective layer over a semiconductor layer; patterning the protective layer to expose areas of the semiconductor layer; depositing an oxide on the exposed areas the semiconductor layer and between portions of the patterned protective layer; etching a portion of the patterned protective layer to expose the semiconductor layer; etching the exposed semiconductor layer to form isolation openings in the semiconductor layer; and filling the isolation openings with a dielectric to form the isolation regions.Type: GrantFiled: April 22, 2020Date of Patent: March 1, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gulbagh Singh, Hsin-Chi Chen, Kun-Tsang Chuang
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Patent number: 11211283Abstract: Bulk semiconductor substrates configured to exhibit semiconductor-on-insulator (SOI) behavior, and corresponding methods of fabrication, are disclosed herein. An exemplary bulk substrate configured to exhibit SOI behavior includes a first isolation trench that defines a channel region of the bulk substrate and a second isolation trench that defines an active region that includes the channel region. The first isolation trench includes a first isolation trench portion and a second isolation trench portion disposed over the first isolation trench portion. A first isolation material fills the first isolation trench portion, and an epitaxial material fills the second isolation trench portion. The epitaxial material is disposed on the first isolation material. A second isolation material fills the second isolation trench. A portion of the bulk substrate underlying the first isolation trench and the channel region is configured to have a higher resistance than the bulk substrate.Type: GrantFiled: June 1, 2020Date of Patent: December 28, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Gulbagh Singh, Kun-Tsang Chuang, Hsin-Chi Chen
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Publication number: 20210375666Abstract: Semiconductor-on-insulator (SOI) field effect transistors (FETs) including body regions having different thicknesses may be formed on an SOI substrate by selectively thinning a region of a top semiconductor layer while preventing thinning of an additional region of the top semiconductor layer. An oxidation process or an etch process may be used to thin the region of the top semiconductor layer, and a patterned oxidation barrier mask or an etch mask may be used to prevent oxidation or etching of the additional portion of the top semiconductor layer. Shallow trench isolation structures may be formed prior to, or after, the selective thinning processing steps. FETs having different depletion region configurations may be formed using the multiple thicknesses of the patterned portions of the top semiconductor layer. For example, partially depleted SOI FETs and fully depleted SOI FETs may be provided.Type: ApplicationFiled: May 28, 2020Publication date: December 2, 2021Inventors: Gulbagh Singh, Po-Jen Wang, Kun-Tsang Chuang
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Patent number: 11183570Abstract: The present disclosure relates to a semiconductor structure includes a substrate with a top surface and first and second devices formed on the top surface of the substrate. The semiconductor structure also includes a deep isolation structure formed in the substrate and between the first and second devices. The deep isolation structure includes a top portion formed at the top surface and having a top width and a bottom surface having a bottom width larger than the top width.Type: GrantFiled: December 30, 2019Date of Patent: November 23, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gulbagh Singh, Tsung-Han Tsai, Kun-Tsang Chuang
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Patent number: 11171199Abstract: The present disclosure relates to an apparatus that includes a bottom electrode and a dielectric structure. The dielectric structure includes a first dielectric layer on the bottom electrode and the first dielectric layer has a first thickness. The apparatus also includes a blocking layer on the first dielectric layer and a second dielectric layer on the blocking layer. The second dielectric layer has a second thickness that is less than the first thickness. The apparatus further includes a top electrode over the dielectric structure.Type: GrantFiled: August 23, 2019Date of Patent: November 9, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Ting Chen, Tsung-Han Tsai, Kun-Tsang Chuang, Po-Jen Wang, Ying-Hao Chen, Chien-Cheng Huang
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Publication number: 20210328031Abstract: The present disclosure relates to a semiconductor structure includes a substrate with a top surface and first and second devices formed on the top surface of the substrate. The semiconductor structure also includes a deep isolation structure formed in the substrate and between the first and second devices. The deep isolation structure includes a top portion formed at the top surface and having a top width and a bottom surface having a bottom width larger than the top width.Type: ApplicationFiled: December 30, 2019Publication date: October 21, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gulbagh SINGH, Tsung-Han TSAI, Kun-Tsang CHUANG
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Publication number: 20210327813Abstract: The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.Type: ApplicationFiled: April 15, 2020Publication date: October 21, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Gulbagh Singh, Kun-Tsang Chuang, Po-Jen Wang
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Publication number: 20210328009Abstract: A semiconductor device includes a substrate, a gate oxide layer formed on the substrate, a gate formed on the gate oxide layer, and a spacer formed adjacent the gate and over the substrate. The spacer includes a void filled with air to prevent leakage of charge to and from the gate, thereby reducing data loss and providing better memory retention. The reduction in charge leakage results from reduced parasitic capacitances, fringing capacitances, and overlap capacitances due to the low dielectric constant of air relative to other spacer materials. The spacer can include multiple layers such as oxide and nitride layers. In some embodiments, the semiconductor device is a multiple-time programmable (MTP) memory device.Type: ApplicationFiled: April 17, 2020Publication date: October 21, 2021Inventors: Gulbagh Singh, Kun-Tsang Chuang, Hsin-Chi Chen
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Patent number: 11145539Abstract: The present disclosure describes a fabrication method that can form air-gaps in shallow trench isolation structures (STI) structures. For example, the method includes patterning a semiconductor layer over a substrate to form semiconductor islands and oxidizing the sidewall surfaces of the semiconductor islands to form first liners on the sidewall surfaces. Further, the method includes depositing a second liner over the first liners and the substrate and depositing a first dielectric layer between the semiconductor islands. The second liner between the first dielectric layer and the first liners is removed to form openings between the first dielectric layer and the first liners. A second dielectric layer is deposited over the first dielectric layer to enclose the openings and form air-gaps between the first dielectric layer and the first liners so that the gaps are positioned along the first liners.Type: GrantFiled: October 18, 2019Date of Patent: October 12, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gulbagh Singh, Hsin-Chi Chen, Kun-Tsang Chuang