Abstract: A quantitative prediction method for gas content of deep marine shale includes: obtaining raw data of known wells; establishing relationship formulas between pore specific surface areas and adsorbed gas contents of a known well in an area as an adsorbed gas content quantitative prediction model; establishing relationship formulas between pore volumes and free gas contents of the known well as a free gas content quantitative prediction model; summing the adsorbed gas contents and corresponding free gas contents to obtain total gas contents; calculating adsorbed gas contents, free gas contents and total gas contents of the known wells; drawing a predicted adsorbed gas content contour map, a predicted free gas content contour map and a predicted total gas content contour map; and reading an adsorbed gas content, a free gas content and a total gas content of an unknown well in the area from the above contour maps.

Abstract: A display apparatus includes: a display; a user input interface; a communicating device; a memory, configured to store computer instructions and data associated with the display and the communicating device; and one or more processor, connected with the display, the user input interface, the communicating device and the memory, and configured to execute the computer instructions to cause the display apparatus to: in response to a target input command received from the user input interface, obtain transmission information of a target audio stream indicated by a target identifier; and send the transmission information to a target playback apparatus, so that the target playback apparatus receives target broadcast isochronous stream, BIS, data broadcasted by the display apparatus from the target transmission channel according to the transmission information.

Abstract: Disclosed are a tungsten hexafluoride preparation method and apparatus based on photoelectric synergy. A photocatalyst and metal tungsten are sequentially filled in a discharge area of a plasma reactor in a direction of gas entry, and the discharge area of the plasma reactor is irradiated with light at the same time; the background gas generates a large amount of plasma in the discharge area, SF6 undergoes decomposition under the synergistic effect of photocatalysis and plasma, SF6 is decomposed to generate fluorine atoms and low-fluorine sulfides such as SF5 and SF4. The generated fluorine ions, SF5, SF4 and low-fluorine sulfides further react with metal tungsten to generate WF6 specialty gas, which not only realizes the utilization of fluorine resources of SF6, but also replaces highly toxic fluorine gas with non-toxic SF6 exhaust gas in the plasma reactor for reaction, thereby ensuring safe operation and low energy consumption.

Abstract: The present disclosure discloses an application development platform and method, a device, and a storage medium. The platform includes: a program development module, configured to display a page editing interface; and generate a page program according to a user's operation on the page editing interface, where the operation includes generating a page layout using materials and components, and configuring page information for the page layout; a mid-end configuration module, configured to configure an application mid-end for the page program; and an application module, configured to integrate the page program and the application mid-end to obtain an application program.

Abstract: A carrying structure is provided and is defined with a main area and a peripheral area adjacent to the main area, where a plurality of packaging substrates are disposed in the main area in an array manner, a plurality of positioning holes are disposed in the peripheral area, and a plurality of positioning traces are formed along a part of the edges of the plurality of positioning holes, such that the plurality of positioning traces are formed with notches. Therefore, a plurality of positioning pins on the machine can be easily aligned and inserted into the plurality of positioning holes by the design of the plurality of positioning traces.

Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A first semiconductor structure including an array of NAND memory strings is formed on a first substrate. A second semiconductor structure including a recess gate transistor is formed on a second substrate. The recess gate transistor includes a recess gate structure protruding into the second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the array of NAND memory strings is coupled to the recess gate transistor across a bonding interface.

Abstract: A method and a system for rendering video images in virtual reality (VR) scenes are provided.

Abstract: A product, in accordance with one aspect of the present invention, includes a porous first layer having a first porosity, and a porous skin layer having a second porosity that is relatively lower than the first porosity. The skin layer is a self-formed layer. A method, in accordance with one aspect of the present invention, includes contacting a resin with a separator. The resin is exposed to radiation for curing the resin, thereby simultaneously creating a porous first layer and a porous skin layer positioned between the first layer and the separator. The first layer has a first porosity. The skin layer has a second porosity that is relatively lower than the first porosity.

Abstract: Methods (200, 1000), network nodes (1100, 1200, 1300, 1400), and computer readable storage media for supporting Ethernet bridging in a user plane are disclosed. The method (200) performed by a first network node (1100, 1200) capable of an Ethernet bridging function includes: obtaining (S201) information on frame detection and forwarding rules for an Ethernet PDU session; and performing (S203) detection and forwarding operations on a frame according to the frame detection and forwarding rules.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

Abstract: A semiconductor device structure and methods of forming the same are described. The structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, and a first gate spacer disposed adjacent the gate dielectric layer, wherein the first gate spacer comprises an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface towards the outer surface of the first gate spacer.

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

Abstract: Provided in the present invention are a magnetic resonance imaging system and method, and a computer-readable storage medium. The method comprises: performing a medical scan of a subject and acquiring a first medical image having a first noise interference artifact, and performing an additional scan of the subject to acquire a second medical image, wherein the second medical image has a second noise interference artifact, and the location mapping of the second noise interference artifact in the first medical image is symmetrical to the location of the first noise interference artifact relative to a pixel center of the first medical image; and performing synthesis-related processing on the first medical image and the second medical image to acquire a post-processed image with reduced noise interference artifacts.

Abstract: A system, multifunctional chip, and fabrication method thereof are provided. For example, a method for use in fabricating an opto-electromechanical system includes generating, from a film of a material and a substrate on which the film is disposed, a suspended portion of the film by removing a first portion of the substrate such that the film's first portion becomes the suspended portion and a second portion of the film is adjacent to a second portion of the substrate after removing the substrate's first portion. A two-dimensional nanomaterial is thereafter transferred onto a section of the suspended portion of the film via an all-dry process. A cantilever is thereafter generated from the film's suspended portion and extends from the film's second portion. The two-dimensional nanomaterial is disposed on the cantilever. Other aspects and features are also claimed and described.

Abstract: Fabrication methods are provided for transforming two-dimensional films into three-dimensional structures based on rolling-up kirigami techniques. In an example, a method includes forming a first layer of a first material on a portion of a substrate, forming a second layer of a second material on the first layer and a second portion of the substrate, and forming a third layer of a third material on a first portion of the second layer. A pattern is formed into the third layer when forming the third layer. The example method further includes transforming at least a portion of the third layer into a three-dimensional structure based in part on removing a second portion of the second layer and at least a portion of the first layer.

Abstract: In its many embodiments, the present invention provides certain 7-, 8-, and 10-substituted amino triazolo quinazoline derivatives of Formula (I): or a pharmaceutically acceptable salt thereof, wherein ring A, R1, R2, and R4 are as defined herein, pharmaceutical compositions comprising one or more such compounds (alone and in combination with one or more other therapeutic agents), and methods for their preparation and use, alone and in combination with other therapeutic agents, as antagonists of A2a and/or A2b receptors, and their use in the treatment of a variety of diseases, conditions, or disorders that are mediated, at least in part, by the adenosine A2a receptor and/or the adenosine A2b receptor.

Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.

Abstract: The invention relates to a ?LED light-emitting and display device with single-ended electrical contact and single-ended carrier injection, and a manufacturing method of the ?LED light-emitting and display device. The ?LED light-emitting and display device comprises more than one pixel unit, and each pixel unit sequentially comprises a lower pixel electrode, ?LED chips, an insulating layer, and an upper pixel electrode from bottom to top, wherein the ?LED chips directly contact with the lower pixel electrode, external carriers are injected into the ?LED chips through the lower pixel electrode, the insulating layer prevents the external carriers from being injected into the ?LED chips through the upper pixel electrode, and the ?LED chips are lit by an alternating electric field applied between the upper pixel electrode and the lower pixel electrode. The invention avoids the complicated bonding process, and is expected to improve the market competitiveness of the ?LED light-emitting and display device.

Abstract: A semiconductor device includes a channel portion disposed on and spaced apart from a substrate, a gate dielectric which includes an upper dielectric region disposed on the channel portion, a first inner gate structure disposed between the substrate and the upper dielectric region, and an outer gate structure including an outer work-function portion and a cap portion. The outer work-function portion covers the upper dielectric region and the first inner gate structure. The cap portion covers the outer work-function portion in a way that the cap portion is separated from the first inner gate structure. The first inner gate structure includes a first work-function material and a conductive material that is different from the first work-function material. The outer work-function portion includes a second work-function material that is different from the conductive material.

Abstract: A magnetic resonance imaging (MRI) scanning system and a method is presented. The method comprises: preconfiguring a plurality of scan configurations, the plurality of scan configurations corresponding to a plurality of scan ranges of a subject to be scanned, and each of the scan configurations comprising an implant-related MRI scan parameter; and executing a scan procedure on the subject to be scanned using at least one of the preconfigured plurality of scan configurations.