Abstract: A method for fabricating a stacked battery structure. The method includes preparing a plurality of battery layers separately, wherein each battery layer includes a substrate, a film battery element fabricated on the substrate and an insulator formed over the film battery element. The insulator has a flat top surface and the film battery element includes a current collector. The method also includes stacking the plurality of battery layers, wherein the insulator of a first battery layer of the plurality of battery layers bonds to the substrate of a second battery layer of the plurality of battery layers by the flat top surface. The method further includes forming a conductive path within the plurality of battery layers, wherein the conductive path connects with at least one of the current collectors of the plurality of battery layers.

Abstract: A method for fabricating a stacked battery structure. The method includes preparing a plurality of battery layers separately, wherein each battery layer includes a substrate, a film battery element fabricated on the substrate and an insulator formed over the film battery element. The insulator has a flat top surface and the film battery element includes a current collector. The method also includes stacking the plurality of battery layers, wherein the insulator of a first battery layer of the plurality of battery layers bonds to the substrate of a second battery layer of the plurality of battery layers by the flat top surface. The method further includes forming a conductive path within the plurality of battery layers, wherein the conductive path connects with at least one of the current collectors of the plurality of battery layers.

Abstract: A method for filling a through hole with solder includes mounting a substrate having a through hole formed therein on a permeable barrier layer having pores that enable gas to flow through the permeable barrier. A solder source is positioned over the through hole. Molten solder is delivered in the through hole with a positive pressure from the solder source such that gas in the through holes passes the permeable barrier while the molten solder remains in the through hole.

Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.

Abstract: A method for filling a through hole with solder includes mounting a substrate having a through hole formed therein on a permeable barrier layer having pores that enable gas to flow through the permeable barrier. A solder source is positioned over the through hole. Molten solder is delivered in the through hole with a positive pressure from the solder source such that gas in the through holes passes the permeable barrier while the molten solder remains in the through hole.

Abstract: Methods for fabricating a via structure are disclosed. In one method, fabricating the via structure includes disposing a stress buffer layer on a first surface of a substrate. The stress buffer layer has an opening aligned to a via hole of the substrate. The method further includes filling the via hole with a conductive material at least up to the first surface of the substrate. The stress buffer layer reduces stress generated due to coefficient of thermal expansion mismatch associated with the via hole and the substrate, and the conductive material extends into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface of the substrate around the via hole.

Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.

Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.

Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.

Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.

Abstract: A technique relating to a battery structure is disclosed. A base substrate and a battery layer having a support substrate are prepared. The battery layer includes a protection layer formed on the support substrate, a film battery element formed on the protection layer and an insulator covering the film battery element. The battery layer is placed onto the base substrate with the bottom of the support substrate facing up. The support substrate is then removed from the battery layer at least in part by etching while protecting the film battery element by the protection layer. A stacked battery structure including the base substrate and the two or more battery layers is also disclosed.

Abstract: A technique relating to a battery structure is disclosed. A base substrate and a battery layer having a support substrate are prepared. The battery layer includes a protection layer formed on the support substrate, a film battery element formed on the protection layer and an insulator covering the film battery element. The battery layer is placed onto the base substrate with the bottom of the support substrate facing up. The support substrate is then removed from the battery layer at least in part by etching while protecting the film battery element by the protection layer. A stacked battery structure including the base substrate and the two or more battery layers is also disclosed.

Abstract: There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip. Furthermore, the chip includes an eaves portion of a predetermined thickness at an outer periphery of the surface, and the underfill forms a fillet extending from a bottom surface of the eaves portion to the surface of the board along a side wall of the chip.

Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.

Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.

Abstract: Methods for depositing material on a chip include forming a mold layer. The mold layer includes one or more openings over respective contact areas, each of the one or more openings having an upper volume and a lower volume. The upper volume has a smaller diameter than a diameter of the lower volume. Each contact area is within the respective lower volume. A material is injected into the one or more openings under pressure.

Abstract: There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip. Furthermore, the chip includes an eaves portion of a predetermined thickness at an outer periphery of the surface, and the underfill forms a fillet extending from a bottom surface of the eaves portion to the surface of the board along a side wall of the chip.

Abstract: A chip pickup system is provided. The chip pickup system includes a detector for detecting a position of an irregular semiconductor chip on a holder. The holder holding plural semiconductor chips in predetermined positions on the holder. The irregular semiconductor chip is out of the predetermined positions. The system further includes a pickup tool for picking up the irregular semiconductor chip at least on the basis of information on the position of the irregular semiconductor chip detected by the detector.

Abstract: Methods for depositing material on a chip include forming a mold layer on a substrate. The mold layer has one or more openings over respective contact areas on the substrate. The one or more openings are formed from an upper volume and a lower volume, the upper volume having a smaller diameter than a diameter of the lower volume. A material is injected into the one or more openings under pressure, such that gas trapped in the one or more openings displaces into the lower volume until the injected material in the one or more openings makes contact with each respective contact area.

Abstract: A method for fabricating a stacked battery structure. The method includes preparing a plurality of battery layers separately, wherein each battery layer includes a substrate, a film battery element fabricated on the substrate and an insulator formed over the film battery element. The insulator has a flat top surface and the film battery element includes a current collector. The method also includes stacking the plurality of battery layers, wherein the insulator of a first battery layer of the plurality of battery layers bonds to the substrate of a second battery layer of the plurality of battery layers by the flat top surface. The method further includes forming a conductive path within the plurality of battery layers, wherein the conductive path connects with at least one of the current collectors of the plurality of battery layers.