Patents by Inventor Kuninori Kawabata
Kuninori Kawabata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8867293Abstract: A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.Type: GrantFiled: March 21, 2013Date of Patent: October 21, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Akinobu Shirota, Kuninori Kawabata
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Patent number: 8472275Abstract: A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.Type: GrantFiled: October 15, 2008Date of Patent: June 25, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Akinobu Shirota, Kuninori Kawabata
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Patent number: 8286054Abstract: In a write operation, an error of regular data read from a regular memory cell is detected and corrected using parity data. A part of the corrected regular data is replaced with write data, to thereby generate new parity data. When write commands are supplied, the parity data starts to be read from a parity memory cell after the read of the regular data is started and while the regular data is read. Further, while the new parity data is supplied to the parity memory cell, the regular data starts to be read from the regular memory cell in response to a following write command. Accordingly, an access cycle time of a semiconductor memory can be reduced.Type: GrantFiled: November 5, 2008Date of Patent: October 9, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Kuninori Kawabata
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Patent number: 8238188Abstract: A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.Type: GrantFiled: February 14, 2011Date of Patent: August 7, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Akinobu Shirota, Kuninori Kawabata
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Publication number: 20120030527Abstract: Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. 1, an external upper limit fetch signal) is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.Type: ApplicationFiled: October 3, 2011Publication date: February 2, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Toshikazu NAKAMURA, Akira KIKUTAKE, Kuninori KAWABATA, Yasuhiro ONISHI, Satoshi ETO
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Patent number: 8078938Abstract: Aspects of the embodiment include providing a semiconductor memory comprising; a plurality of memory blocks that includes a plurality of regular memory cells; a plurality of first parity blocks that are disposed in accordance with the plurality of memory blocks, wherein the plurality of first parity blocks include a first parity memory cell holding a first parity code; a second parity block that includes a second parity memory cell holding a second parity code having a parity bit corresponding to the first parity code; a parity error correction unit that corrects an error of the first parity code using the second parity code; and a data error correction unit that corrects an error of the data stored in a regular memory cell using the first parity code corrected by the parity error correction unit.Type: GrantFiled: May 27, 2008Date of Patent: December 13, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Kuninori Kawabata
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Publication number: 20110134714Abstract: A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.Type: ApplicationFiled: February 14, 2011Publication date: June 9, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Akinobu SHIROTA, Kuninori Kawabata
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Patent number: 7916568Abstract: A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.Type: GrantFiled: November 3, 2008Date of Patent: March 29, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Akinobu Shirota, Kuninori Kawabata
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Patent number: 7911874Abstract: An interface conversion macro converts a signal compliant with a system interface specification output from a controller to a signal compliant with a memory interface specification, and outputs the same to a memory interface part, and it also converts a signal output from the memory macro to a signal compliant with the system interface specification and outputs the same to the controller. By converting the system interface specification and the memory interface specification to each other by an interface conversion macro, a common memory macro can be mounted on a semiconductor integrated circuit even when the system interface specification differs. Accordingly, when designing a system, the design verification time, evaluation time, and test time of the semiconductor integrated circuit can be reduced. As a result, the design time and design cost of the semiconductor integrated circuit can be reduced.Type: GrantFiled: May 29, 2008Date of Patent: March 22, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Kuninori Kawabata, Yoshiyuki Ishida, Satoshi Eto
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Publication number: 20100321983Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.Type: ApplicationFiled: March 5, 2010Publication date: December 23, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
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Patent number: 7827463Abstract: In a semiconductor memory device having an error-correction function: one or both of a portion of a set of data bits and a set of parity bits based on the set of data bits are held, where the set of data bits and the set of parity bits constitute a code for error correction and are written in memory cells in the leading write cycle in a burst write operation. The set of parity bits written in memory cells in the leading write cycle is updated in the final write cycle on the basis of the portion of the set of data bits and/or the set of parity bits, and another set of data bits required to be written in the final write cycle in the memory cells at the address at which the above portion is written in the leading write cycle.Type: GrantFiled: November 10, 2005Date of Patent: November 2, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Shuzo Otsuka, Kuninori Kawabata, Toshikazu Nakamura, Akira Kikutake
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Patent number: 7818516Abstract: A memory controller connected to memory includes: an address reception unit for receiving an address code externally input together with a command; and a command conversion unit for outputting to the memory an MRS command to change the internal settings of the memory based on the address code when the address code input together with a first command specifies an address space for which the memory is not implemented.Type: GrantFiled: May 30, 2006Date of Patent: October 19, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Kuninori Kawabata, Satoshi Eto, Toshiya Miyo
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Publication number: 20100220540Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.Type: ApplicationFiled: March 5, 2010Publication date: September 2, 2010Applicant: FUJISU MICROELECTRONICS LIMITEDInventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
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Patent number: 7706209Abstract: A semiconductor device, including a word line driver for driving a word line connected to a memory cell in a memory cell array and for resetting the word line when the memory cell changes from an activated to a standby state. The reset level of the word line driver is set when resetting of the word line is performed, and may be switched between first and second potentials. A word line reset level generating circuit varies the amount of negative potential current supply in accordance with memory cell array operating conditions. The semiconductor device includes a plurality of power source circuits, each having an oscillation circuit and a capacitor, for driving the capacitor via an oscillation signal outputted by the oscillation circuit. At least some power source circuits share a common oscillation circuit, and different capacitors are driven via the common oscillation signal.Type: GrantFiled: December 22, 2005Date of Patent: April 27, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Masato Takita, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masatomo Hasegawa, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii, Shinichi Yamada, Kaoru Mori
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Patent number: 7675800Abstract: When a main block address held in a memory refresh address counter coincides with an access block address corresponding to an access request, its counter value is transferred to a sub refresh address counter. Thereafter, a sub refresh address counter operates with priority over a main refresh address counter until its counter value reaches a final value. Consequently, an access operation and a refresh operation can be simultaneously executed without interfering with each other. As a result, it is possible to execute the refresh operation with a minimum increase in circuit scale and without any deterioration in access efficiency.Type: GrantFiled: February 28, 2008Date of Patent: March 9, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Kuninori Kawabata
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Patent number: 7599244Abstract: A semiconductor memory for inputting and outputting data synchronously with a clock includes a clock reception unit for receiving the clock, and a command reception unit for initially receiving a first specific command synchronizing with the clock after turning a power on, after a low-power standby or after an initialization, followed by starting a command reception.Type: GrantFiled: May 22, 2006Date of Patent: October 6, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Satoshi Eto, Kuninori Kawabata, Toshiya Miyo, Yuji Serizawa
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Patent number: 7548468Abstract: A bit line resetting signal is supplied to the gate of an nMOS transistor (or a precharge circuit) which connects a bit line with a precharge voltage line. The high-level voltage of the bit line resetting signal is retained at a first voltage during the precharge operation after a refresh operation, and is retained at a second voltage higher than the first voltage during the precharge operation after an access operation. In the precharge operation after the refresh operation, therefore, the second voltage is not used so that the current consumption of the generating circuit of the second voltage is reduced. Thus, it is possible to reduce the current consumption (or the standby current) during the standby period for which the internal refresh requests continuously occur.Type: GrantFiled: August 24, 2006Date of Patent: June 16, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Kuninori Kawabata, Shuzo Otsuka
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Publication number: 20090119567Abstract: In a write operation, an error of regular data read from a regular memory cell is detected and corrected using parity data. A part of the corrected regular data is replaced with write data, to thereby generate new parity data. When write commands are supplied, the parity data starts to be read from a parity memory cell after the read of the regular data is started and while the regular data is read. Further, while the new parity data is supplied to the parity memory cell, the regular data starts to be read from the regular memory cell in response to a following write command. Accordingly, an access cycle time of a semiconductor memory can be reduced.Type: ApplicationFiled: November 5, 2008Publication date: May 7, 2009Applicant: FUJITSU LIMITEDInventor: Kuninori Kawabata
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Publication number: 20090077432Abstract: Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. 1, an external upper limit fetch signal) is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.Type: ApplicationFiled: November 18, 2008Publication date: March 19, 2009Applicant: FUJITSU LIMITEDInventors: Toshikazu Nakamura, Akira Kikutake, Kuninori Kawabata, Yasuhiro Onishi, Satoshi Eto
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Publication number: 20090052265Abstract: A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.Type: ApplicationFiled: November 3, 2008Publication date: February 26, 2009Applicant: FUJITSU LIMITEDInventors: Akinobu SHIROTA, Kuninori Kawabata