Abstract: An electronic device includes a first circuit which refers to an external clock and thus produces a first internal clock, and a second circuit which refers to the first internal clock and thus produces a second internal clock. The first circuit has a first phase error between the external clock and the first internal clock, and the second circuit has a second phase error between the first internal clock and the second internal clock. The first phase error has a sign reverse to that of the second phase error.

Abstract: According to the present invention, a semiconductor memory device includes an oscillator for generating with a predetermined cycle a timing signal for performing a refresh operation for the memory cell array. The oscillator includes an oscillation circuit, for receiving a predetermined characteristic value and generating the timing signal having the cycle in accordance with the characteristic value; a characteristic value generation circuit, having a programmable memory for generating an adjustment signal for an adjustment of the characteristic value, for transmitting to the oscillation circuit the characteristic value adjusted in accordance with the adjustment signal; and a confirmation switch for generating, instead of the memory, the adjustment signal for a test in accordance with a test entry signal.