Patents by Inventor Kunio Uchiyama
Kunio Uchiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6272596Abstract: A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has an output the instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executor executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.Type: GrantFiled: September 15, 1999Date of Patent: August 7, 2001Assignees: Hitachi, Ltd., Hitachi Micro Computer Engineering, Ltd.Inventors: Tadahiko Nishimukai, Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki, Makoto Hanawa
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Patent number: 6260107Abstract: A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.Type: GrantFiled: March 8, 2000Date of Patent: July 10, 2001Assignee: Hitachi, LTDInventors: Kunio Uchiyama, Osamu Nishii
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Publication number: 20010004218Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Type: ApplicationFiled: January 23, 2001Publication date: June 21, 2001Applicant: Hitachi, Ltd.Inventors: Masashi Horiguchi, Kunio Uchiyama, Kiyoo Itoh, Takeshi Sakata, Masakazu Aoki, Takayuki Kawahara
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Patent number: 6175251Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Type: GrantFiled: April 15, 1999Date of Patent: January 16, 2001Assignee: Hitachi, Ltd.Inventors: Masashi Horiguchi, Kunio Uchiyama, Kiyoo Itoh, Takeshi Sakata, Masakazu Aoki, Takayuki Kawahara
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Patent number: 6107836Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Type: GrantFiled: November 25, 1998Date of Patent: August 22, 2000Assignee: Hitachi, Ltd.Inventors: Takayuki Kawahara, Ryoichi Hori, Masashi Horiguchi, Ryoichi Kurihara, Kiyoo Itoh, Masakazu Aoki, Takeshi Sakata, Kunio Uchiyama
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Patent number: 6092172Abstract: A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.Type: GrantFiled: October 15, 1997Date of Patent: July 18, 2000Assignee: Hitachi, Ltd.Inventors: Junichi Nishimoto, Osamu Nishii, Fumio Arakawa, Susumu Narita, Masayuki Ito, Makoto Toda, Kunio Uchiyama
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Patent number: 6078986Abstract: A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.Type: GrantFiled: August 13, 1996Date of Patent: June 20, 2000Assignee: Hitachi, Ltd.Inventors: Kunio Uchiyama, Osamu Nishii
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Patent number: 6046604Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Type: GrantFiled: July 28, 1998Date of Patent: April 4, 2000Assignee: Hitachi, Ltd.Inventors: Masashi Horiguchi, Kunio Uchiyama, Kiyoo Itoh, Takeshi Sakata, Masakazu Aoki, Takayuki Kawahara
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Patent number: 6012139Abstract: A Floating Point Unit (FPU) with a sixteen-bit fixed length instruction set for thirty-two bit data. The FPU operates as part of RISC microprocessor. The CPU does all memory addressing. Furthermore, data between the CPU and the FPU is transferred via a communication register. An FPU pipeline is synchronized with a CPU pipeline. The sixteen-bit fixed length instruction group has special instructions for immediate loading of a floating point zero and/or a floating point one. Two instructions are dedicated for this purpose. Furthermore, the 16-bit fixed length instruction group of the FPU flushes denormalized numbers to zero. The instruction set also rounds floating point numbers to zero. An FMAC instruction of the instruction set has the capability to accumulate into a different register for consecutive FMAC operations.Type: GrantFiled: January 31, 1996Date of Patent: January 4, 2000Assignee: Hitachi Micro Systems, Inc.Inventors: Prasenjit Biswas, Shumpei Kawasaki, Norio Nakagawa, Osamu Nishii, Kunio Uchiyama
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Patent number: 5974533Abstract: A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.Type: GrantFiled: July 10, 1998Date of Patent: October 26, 1999Assignees: Hitachi, Ltd., Hitachi Micro Computer Engineering, Ltd.Inventors: Tadahiko Nishimukai, Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki, Makoto Hanawa
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Patent number: 5880604Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Type: GrantFiled: September 17, 1996Date of Patent: March 9, 1999Assignee: Hitachi, Ltd.Inventors: Takayuki Kawahara, Ryoichi Hori, Masashi Horiguchi, Ryoichi Kurihara, Kiyoo Itoh, Masakazu Aoki, Takeshi Sakata, Kunio Uchiyama
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Patent number: 5860000Abstract: An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.Type: GrantFiled: January 31, 1996Date of Patent: January 12, 1999Assignee: Hitachi Micro Systems, Inc.Inventors: Prasenjit Biswas, Gautam Dewan, Kevin Iadonato, Norio Nakagawa, Kunio Uchiyama
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Patent number: 5828235Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Type: GrantFiled: May 24, 1996Date of Patent: October 27, 1998Assignee: Hitachi, Ltd.Inventors: Masashi Horiguchi, Kunio Uchiyama, Kiyoo Itoh, Takeshi Sakata, Masakazu Aoki, Takayuki Kawahara
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Patent number: 5809274Abstract: A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instructioon is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output the instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.Type: GrantFiled: July 1, 1997Date of Patent: September 15, 1998Assignees: Hitachi, Ltd., Hitachi Micro Computer Engineering, Ltd.Inventors: Tadahiko Nishimukai, Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki, Makoto Hanawa
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Patent number: 5680631Abstract: A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output; and an instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.Type: GrantFiled: November 18, 1992Date of Patent: October 21, 1997Assignees: Hitachi, Ltd., Hitachi Micro Computer Engineering, Ltd.Inventors: Tadahiko Nishimukai, Atsushi Hasegawa, Kunio Uchiyama, Ikuya Kawasaki, Makoto Hanawa
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Patent number: 5614847Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Type: GrantFiled: August 24, 1994Date of Patent: March 25, 1997Assignee: Hitachi, Ltd.Inventors: Takayuki Kawahara, Ryoichi Hori, Masashi Horiguchi, Ryoichi Kurihara, Kiyoo Itoh, Masakazu Aoki, Takeshi Sakata, Kunio Uchiyama
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Patent number: 5583457Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Type: GrantFiled: February 8, 1994Date of Patent: December 10, 1996Assignee: Hitachi, Ltd.Inventors: Masashi Horiguchi, Kunio Uchiyama, Kiyoo Itoh, Takeshi Sakata, Masakazu Aoki, Takayuki Kawahara
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Patent number: 5574876Abstract: A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a node register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.Type: GrantFiled: September 9, 1993Date of Patent: November 12, 1996Assignee: Hitachi, Ltd.Inventors: Kunio Uchiyama, Osamu Nishii
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Patent number: 5555394Abstract: In a data processor intended for fast partial clearing of a buffer memory which is based on a direct map scheme or a set associative scheme, a latch holds a comparison value used for partial clearing of the buffer memory, a comparator compares a tag read out of a tag array with the comparison value and asserts the clear signal in response to detection of the coincidence of both values, and a control logic circuit produces a hit signal and a new V flag from the old V flag, a coincidence signal, a clear signal and a type signal. In response to the detection of coincidence of values by the comparator, the V flag of a corresponding entry is shifted from the clear waiting state to the invalid state.Type: GrantFiled: September 2, 1993Date of Patent: September 10, 1996Assignee: Hitachi, Ltd.Inventors: Fumio Arakawa, Kunio Uchiyama
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Patent number: 5454087Abstract: An address of a branch instruction, a branch target address thereof, and a type thereof are stored as branch history information in a branch instruction buffer. In addition, a return address for a return from a subroutine is retained in a return buffer. A look-up operation is conducted through the buffer by using the pre-fetch address such that when a hit occurs, a branch target address is output from the buffer depending on a branch instruction type. Consequently, the branch processing is achieved at a high speed. Particularly, the processing speed of an unconditional branch instruction containing a return instruction is increased.Type: GrantFiled: October 23, 1992Date of Patent: September 26, 1995Assignee: Hitachi, Ltd.Inventors: Susumu Narita, Fumio Arakawa, Kunio Uchiyama, Hirokazu Aoki