Abstract: An instruction fetch unit IU in a microprocessor capable of decoding two instructions in parallel fetches first and second instructions of the shortest instructions in one cycle. The fetched first instruction is supplied to and decoded by a first instruction decoder ID0, while the fetched second instruction is supplied to and decoded by a second instruction decoder ID1. In a case where an instruction having a bit width longer than the shortest instruction has been fetched by the instruction fetch unit IU, information to be decoded by the second instruction decoder ID1 is the non-head code of the instruction, and hence, a pipeline control unit PCNT invalidates the decoded result of the second instruction decoder ID1. Thus, it is permitted to decode the two shortest instructions in parallel, and to eliminate the erroneous information of the decoded result of the second decoder in the case of the fetch of the non-shortest instruction.

Abstract: A data processor in which, when two primitive instructions are decoded by instruction decoders, a microprogram ROM is not used under the control of a selector, and the two primitive instructions are executed in parallel by instruction execution units in accordance with the decoded outputs of the instruction decoders. When a high performance instruction is decoded by one of the instruction decoders, at a first step processing, one of the instruction execution units selects the output of the one instruction decoder to execute the instruction. At a second step processing, the one instruction execution unit selects a microinstruction of the microprogram ROM and executes the instruction. It is therefore unnecessary to use the microprogram ROM for the execution of a primitive instruction and a high performance instruction at the first step processing, thereby reducing the capacity, area and power consumption of the microprogram ROM.

Abstract: The semiconductor device has more-significant global data lines and less-significant data lines hierarchically formed, and switches for controlling the more-significant global data lines and the less-significant data lines to be connected each other. In addition, the semiconductor device has the unit for precharging the global data lines independently of the data lines.

Abstract: A data processor is used with a main memory that stores operand data and instructions. The data processor itself includes two cache memories, one of which stores logical instruction addresses and corresponding instructions while the other stores logical operand addresses and corresponding operand data. A selector chooses whether a logical operand address or logical instruction address should access the respective cache memory or the main memory to obtain an instruction or operand data. Furthermore, the processor includes the capability of invalidating all of the data in either the instruction cache memory or operand cache memory based on a software instruction signal received at a purge unit.

Abstract: A data processor is provided with a first register storing a first half word of one instruction; a second register storing a second half word of the instruction; a first decoder decoding the first half word and at the same time detecting whether there exists an addressing extension portion between the first half word and the second half word; a second decoder decoding the second half word; and, a decode result generating circuit, to which a detection signal of the first decoder indicates whether the addressing extension portion exists. A decode result of the first decoder and a decode result of the second decoder are supplied to the decode result generating circuit. An extension portion register is provided to store the addressing extension portion. When the first decoder detects the addressing extension portion, the decode result generating circuit invalidates the decode result of the second decoder.

Abstract: A non-shared system with respect to an outside and an inside cache in a multi-processor system has multi-layer hierarchical cache. An invalidation address on a main memory address bus 31 in company with the rewriting of a main memory 30 is transmitted via a first and a second path 35, 36 to inside caches 11,21 so as to invalidate these inside caches 11, 21. The invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and outside caches 12, 22 so as to invalidate these outside caches 12, 22. It is extremely improbable for the address of access for writing to the transmitted to the main memory address bus 31 because the outside caches 12, 22 are operated in either copy back or write once system.

Abstract: Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating signal to the address bus and the invalidating signal line, respectively.

Abstract: A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and on output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

Abstract: A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory, and an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory the instruction control unit produces an output to be executed. An instruction execution unit has a second associative memory that stores operand data read out from the main memory, and an instruction executioner executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

Abstract: In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

Abstract: A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and an output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

Abstract: In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

Abstract: A main memory is subdivided into a shared region to undergo a write access from a plurality of processors and an input/output device and a plurality of private regions to undergo a write access only from the associated processor. Each of the cache devices includes a region discriminating circuit for determining whether an address generated from the processor is to be employed for an access to the shared region or to the private regions. If the access is to be conducted to the shared region, the cache devices operate according to the write-through method. On the other hand, if the access is to be conducted to the private region, the cache devices operate according to the copy-back method. When the processor or the input/output device rewrites data in the shared region of the main memory, the stored data of the shared region in the cache device of the processor is invalidated.

Abstract: A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory, and the instruction control unit also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory. The instruction controller provides the instruction to be executed as an output. The data processor further includes an instruction execution unit having a second associative memory storing operand data read out from the main memory, and an instruction execution unit that executes the instruction.

Abstract: A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instruction read out from the main memory, and an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory the instruction control unit produces an output the instruction to be executed. An instruction execution unit has a second associative memory that stores operand data read out from the main memory, and an instruction executioner executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

Abstract: A cache memory contained in a processor features a high efficiency in spite of its small capacity.In the cache memory control circuit, it is detected whether the access operation of the processor is directed to a particular region of the memory, and when the data is to be read out from, or is to be written onto, the particular region, the data is copied onto the cache memory and when the data is to be read out from other regions, operation of the memory is executed immediately without waiting for the reference of cache memory.By assigning the particular region for the data that is to be used repeatedly, it is possible to provide a cache memory having good efficiency in spite of its small capacity. A representative example of such data is the data in a stack.

Abstract: The present invention relates to a pipeline data processing apparatus wherein an instruction is fetched from a main storage, the instruction is decoded to generate control information for executing the instruction, and the control information is transferred to an instruction execute circuit. The target address of a branch instruction is stored in the index field of an associative memory, and control information obtained by decoding a target instruction of branch corresponding to the branch instruction is stored in the data field of the associative memory beforehand. When executing the branch instruction, the associative memory is accessed with the target address, and the control information of the corresponding entry is read out and is transferred to the instruction execute circuit, whereupon the instruction execute circuit starts executing the target instruction of branch instruction in succeession to the execution of the branch instruction.

Abstract: In a buffer memory, a validity flag to be added to each data portion is stored in a tag array or address section at a location corresponding to each data portion. After determining whether each validity flag is to be used as a search object, based upon the data portion to be accessed during searching the tag array and an access mode, the address and its validity flag are simultaneously searched. The logical sum of each output of the search result on a word coincidence line becomes a hit judgement signal.

Abstract: A register recovering system for a data processor having a group of general-purpose registers includes a saving register for saving the content of the general-purpose register; a control register for storing discrimination information for the general-purpose register; a setting unit for setting the discrimination information at the control register, based on instruction information of a machine code to be processed by the data processor; and a setting unit for setting the content of the saving register to the general-purpose register in accordance with the discrimination information stored in the control register.

Abstract: Herein disclosed is a method of controlling a microprocessor in accordance with the present invention characterized in that, when the microprocessor for executing a microprogram in accordance with clock cycles .PHI..sub.1 and .PHI..sub.2 receives a command (i.e., STOP signal) for stopping a normal operation from the outside, a freezing signal (i.e., FRZ signal) synchronizing with the clock cycles is generated to bring the operation being executed into a stopped state.