Abstract: A fluorinated polyvalent carbonyl compound is produced by an economically advantageous method from inexpensive materials without requiring a complicated synthetic process step. Namely, the present invention comprises reacting a polyvalent alcohol having at least two kinds of alcohol skeletons selected among a primary alcohol, a secondary alcohol and a tertiary alcohol, with an acid halide to obtain a polyvalent ester compound, fluorinating it in a liquid phase to obtain a perfluorinated polyvalent ester compound, and cleaving the ester bonds derived from primary and secondary alcohols in the perfluoropolyvalent ester compound to obtain a fluorinated polyvalent carbonyl compound.

Abstract: A process for manufacturing a semiconductor wafer which has superior suitability for mass production and reproducibility. The process comprises the steps of preparing a first member which has a monocrystalline semiconductor layer on a semiconductor substrate with a separation layer arranged therebetween with a semiconductor wafer as the raw material, transferring the monocrystalline semiconductor layer onto a second member which comprises a semiconductor wafer after separating the monocrystalline semiconductor layer through the separation layer, and smoothing the surface of the semiconductor substrate after the transferring step so as to be used as a semiconductor wafer for purposes other than forming the first and second members.

Abstract: The present invention provides a process whereby fluorinated ketones of various structures can be produced by short process steps and which is useful as an industrial production process.

Abstract: The present invention provides novel processes for preparing a fluorinated acyl fluoride and a fluorinated vinyl ether.

Abstract: The present invention produces an unsaturated compound (Formula 2) useful as a fluororesin starting material and the like by using a compound of the Formula 1 as a starting material.

Abstract: The present invention provides a method for obtaining a compound useful as a raw material for various fluororesins in high yield by a short process by using a starting material which is inexpensive and readily available.

Abstract: The invention provides a process for producing a fluorine-containing compound from an inexpensive material. Namely, Compound I such as RACH2OH is reacted with Compound II such as XCORB to form Compound III such as RACH2OCORB, followed by fluorination in a liquid phase to form Compound IV such as RAFCF2OCORBF, which is converted to Compound V such as RAFCOF and/or Compound VI such as RBFCOF. RA is an alkyl group or the like, RB is a perhalogenoalkyl group or the like, RAF and RBF are fluorinated RA and RB, and X is halogen.

Abstract: A semiconductor device may include a fuse section 100 having a layer in which a plurality of fuses 26 that are fusible by irradiation of an energy beam are formed, and a circuit wiring layer 200 formed in the fuse section 100. The circuit wiring layer 200 is disposed in a layer below the layer in which the fuses 26 are formed, and is not connected to the fuses 26.

Abstract: A half tone mask of the present invention is provided with a half tone film in which a thickness of the half tone film in a dense pattern area where optical proximity effect occurs differs from that in an isolated pattern area where the optical proximity effect does not occur, the thickness of the half tone film in the isolated pattern area being adjusted so that difference in size of a resist does not occur between the dense pattern area and the isolated pattern area due to the optical proximity effect, thus preventing the difference in size of the resist between the dense pattern area and the isolated pattern area, even when providing high definition patterns which causes the optical proximity effect.

Abstract: A semiconductor memory device (SRAM) comprises memory cells, each of which includes two load transistors, two driver transistors and two transfer transistors. The SRAM cell includes a semiconductor substrate in which the transistors are formed, a first interlayer dielectric formed on the semiconductor substrate, first contact portions formed in the first interlayer dielectric and first wiring layers (node wiring layers and pad layers) formed on the first interlayer dielectric. The first contact portions and the first wiring layers include metal layers made of refractory metal and a refractory metal nitride layers. This semiconductor memory device of the present invention is capable of enhancing an integration degree of wiring layers and achieving a microfabrication.

Abstract: Semiconductor devices are provided that include a memory cell having load transistors, driver transistors, and transfer transistors. The semiconductor device has a first element-forming region that can be provided in, for example, a p-well region. The first element-forming region can include includes a first active region, a second active region, a third active region, a fourth active region and a fifth active region. The third active region, the fourth active region and the fifth active region can be provided between the first active region and the second active region. The first active region and the second active region can be continuous with the third active region, the fourth active region and the fifth active region, respectively. Thus, semiconductor devices can be provided having element-forming regions that can be readily formed. Memory systems and electronic equipment that include such semiconductor devices can also be provided.

Abstract: A semiconductor device having a memory cell including first and second load transistors, first and second driver transistors, and first and second transfer transistors. The semiconductor device includes a first gate-gate electrode layer and a first drain-gate wiring layer. A distance L1 between the edges of the first drain-gate wiring layer and an active region of the first driver transistor is greater than or equal to a distance L2 between the first drain-gate wiring layer and an active region of the first load transistor. This structure provides semiconductor devices in which memory cells having desired characteristics can be readily fabricated. The invention also provides memory systems and electronic apparatuses which include the above semiconductor devices.

Abstract: A semiconductor device having a memory cell including first and second load transistors, first and second driver transistors, and first and second transfer transistors. The semiconductor device includes first and second gate-gate electrode layers, first and second drain-drain wiring layers, and first and second drain-gate wiring layers. The first drain-gate wiring layer and the second drain-gate wiring layer are located in different layers. The first drain-gate wiring layer is located below the first drain-drain wiring layer, and the second drain-gate wiring layer is located in above the first drain-drain wiring layer. This structure provides a semiconductor device that has reduced cell area. The invention also provides a memory system and electronic apparatus that include the above semiconductor device.

Abstract: A semiconductor device has a semiconductor substrate having a peripheral circuit area and a memory cell area. A border region having a well of a first conductivity is formed between the peripheral circuit area and the memory cell area. A well of a second conductivity is formed in the peripheral circuit area. The well in the peripheral circuit area is in contact with the border region but not in contact with the memory cell area. Dummy transistors are formed in the border region. The dummy transistors are arranged with substantially the same transistor forming density as that of the memory cell area.

Abstract: A method of producing a semiconductor member comprises a first step of preparing a first member having a non-porous layer on a semiconductor substrate, and a second step of transferring the non-porous layer from the first member onto a second member, wherein use of the semiconductor substrate from which the non-porous layer is separated in the second step as a constituent material of the first member in the first step is conducted (n−1) times (“n” is a natural number not less than 2), the first and second steps are repeated n times, the semiconductor substrate is separated in n-th use in the second step and the separated semiconductor substrate is used for an use other than that of the first and second steps.

Abstract: The semiconductor device has an insulated-gate field-effect transistor (MOS transistor), a bipolar transistor, and a Zener diode. The MOS transistor is formed in a well of a first conductive type (p-type) and has a gate insulation layer, a gate electrode, side wall insulation layers, and second conductive type (n-type) of source and drain regions. The bipolar transistor has the drain region as a collector region, the well as a base region, and an n-type impurity-diffusion layer isolated from the drain region as an emitter region. The Zener diode is formed by the junction of an n-type impurity-diffusion layer continuous with the drain region and a p-type impurity-diffusion layer. The source and drain regions have a silicide layer formed on the surface thereof. A protection layer is formed on the surface of the n-type impurity-diffusion layer of the Zener diode.

Abstract: A semiconductor device is provided with an SRAM memory cell. The semiconductor device includes a first gate-gate electrode layer, a second gate-gate electrode layer, a first drain-drain wiring layer, a second drain-drain wiring layer, a first drain-gate wiring layer and second drain-gate wiring layers. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively. A first protruded active region is provided in a manner to protrude from an end portion of the first active region.

Abstract: A semiconductor device is provided with an SRAM memory cell. The semiconductor device includes a first gate-gate electrode layer, a second gate-gate electrode layer, a first drain-drain wiring layer, a second drain-drain wiring layer, a first drain-gate wiring layer and a second drain-gate wiring layer. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively. The diameter of a through hole in the first interlayer dielectric layer is equal to or less than the diameter of through holes in the second and third interlayer dielectric layers.

Abstract: A semiconductor device is provided with an SRAM memory cell. The semiconductor device includes a first gate-gate electrode layer, a second gate-gate electrode layer, a first drain-drain wiring layer, a second drain-drain wiring layer, a first drain-gate wiring layer and second drain-gate wiring layers. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively. The width of the first gate-gate electrode layer in the first load transistor is larger than the width of the first gate-gate electrode layer in the first driver transistor.

Abstract: A semiconductor device is provided with an SRAM memory cell. The semiconductor device includes a first gate-gate electrode layer, a second gate-gate electrode layer, a first drain-drain wiring layer, a second drain-drain wiring layer, a first drain-gate wiring layer and a second drain-gate wiring layer. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively. The upper layer is provided above either an n-type well region or a p-type well region.