Patents by Inventor Kuo Cheng Wang
Kuo Cheng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942548Abstract: A multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer.Type: GrantFiled: May 18, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H. Diaz, Chih-Hao Wang, Wai-Yi Lien, Ying-Keung Leung
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Patent number: 11942476Abstract: A method includes forming a semiconductor fin on a substrate; conformally forming a dielectric layer over the semiconductor fin; depositing an oxide layer over the dielectric layer; etching back the oxide layer to lower a top surface of the oxide layer to a level below a top surface of the semiconductor fin; conformally forming a metal oxide layer over the semiconductor fin, the dielectric layer, and the etched back oxide layer; planarizing the metal oxide layer and the dielectric layer to expose the semiconductor fin; forming a gate structure extending across the semiconductor fin; forming source/drain regions on the semiconductor fin and on opposite sides of the gate structure.Type: GrantFiled: July 15, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Chih-Hao Wang
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Patent number: 11942513Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.Type: GrantFiled: January 10, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Jui-Chien Huang
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Patent number: 11942478Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.Type: GrantFiled: May 6, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Guan-Lin Chen
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Publication number: 20240096895Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
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Publication number: 20240096882Abstract: A semiconductor structures and a method for forming the same are provided. The semiconductor structure includes first nanostructures and second nanostructures spaced apart from the first nanostructures in a first direction. A left-most point of the first nanostructures and a left-most point of the second nanostructures has a first distance in the first direction. The semiconductor structure further includes first source/drain features attached to opposite sides of the first nanostructures in a second direction being orthogonal to the first direction and third nanostructures and fourth nanostructures spaced apart from the third nanostructures in the first direction. A left-most point of the third nanostructures and a left-most point of the fourth nanostructures has a second distance in the first direction. In addition, the third nanostructures are wider than the first nanostructures in the first direction, and the first distance is smaller than the second distance.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Han LIU, Chih-Hao WANG, Kuo-Cheng CHIANG, Shi-Ning JU, Kuan-Lun CHENG
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Publication number: 20240096880Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.Type: ApplicationFiled: November 16, 2023Publication date: March 21, 2024Inventors: Mao-Lin Huang, Chih-Hao Wang, Kuo-Cheng Chiang, Jia-Ni Yu, Lung-Kun Chu, Chung-Wei Hsu
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Publication number: 20240096994Abstract: A method for forming a semiconductor device is provided. The method includes forming a plurality of first channel nanostructures and a plurality of second channel nanostructures in an n-type device region and a p-type device region of a substrate, respectively, and sequentially depositing a gate dielectric layer, an n-type work function metal layer, and a cap layer surrounding each of the first and second channel nanostructures. The cap layer merges in first spaces between adjacent first channel nanostructures and merges in second spaces between adjacent second channel nanostructures. The method further includes selectively removing the cap layer and the n-type work function metal layer in the p-type device region, and depositing a p-type work function metal layer over the cap layer in the n-type device region and the gate dielectric layer in the p-type device region. The p-type work function metal layer merges in the second spaces.Type: ApplicationFiled: February 10, 2023Publication date: March 21, 2024Inventors: Lung-Kun CHU, Jia-Ni YU, Chun-Fu LU, Mao-Lin HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
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Patent number: 11935921Abstract: A semiconductor device includes a substrate and a semiconductor structure over the substrate. The semiconductor device also includes a first dielectric structure over the substrate, and the first dielectric structure has a first height. The semiconductor device further includes a second dielectric structure over the substrate, and the second dielectric structure has a second height. The second height is smaller than the first height. In addition, the semiconductor device includes a first gate stack wrapped around the first dielectric structure, and the semiconductor structure and the second dielectric structure are spaced apart from the first gate stack. The semiconductor device includes a second gate stack wrapped around the second dielectric structure and the semiconductor structure, and the second gate stack is electrically isolated from the first gate stack.Type: GrantFiled: June 22, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240088145Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.Type: ApplicationFiled: November 27, 2023Publication date: March 14, 2024Inventors: Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu, Chih-Hao Wang, Kuo-Cheng Ching
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Publication number: 20240088026Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.Type: ApplicationFiled: January 17, 2023Publication date: March 14, 2024Inventors: Yi Ching Ong, Wei-Cheng Wu, Chien Hung Liu, Harry-Haklay Chuang, Yu-Sheng Chen, Yu-Jen Wang, Kuo-Ching Huang
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Patent number: 11929413Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first channel structure and a second channel structure over a substrate. The semiconductor device structure also includes a first gate stack over the first channel structure, and the first gate stack has a first width. The semiconductor device structure further includes a second gate stack over the second channel structure. The second gate stack has a protruding portion extending away from the second channel structures. The protruding portion of the second gate stack has a second width, and half of the first width is greater than the second width.Type: GrantFiled: July 22, 2022Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-Chuan You, Huan-Chieh Su, Kuo-Cheng Chiang, Chih-Hao Wang
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Patent number: 11923361Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor fin over a substrate and multiple semiconductor nanostructures suspended over the semiconductor fin. The semiconductor device structure also includes a gate stack extending across the semiconductor fin, and the gate stack wraps around each of the semiconductor nanostructures. The semiconductor device structure further includes a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. In addition, the semiconductor device structure includes an isolation structure between the semiconductor fin and the gate stack. The isolation structure extends exceeding opposite sidewalls of the first epitaxial structure.Type: GrantFiled: July 5, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shi-Ning Ju, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240072147Abstract: A semiconductor device includes a substrate, a shallow trench isolation structure, two epitaxial structures, one or more semiconductor channel layers, a gate metal layer and a gate spacer. The shallow trench isolation structure is disposed over the substrate. The epitaxial structures are disposed over the shallow trench isolation structure. The one or more semiconductor channel layers connect the two epitaxial structures. The gate metal layer is located between the epitaxial structures and engages the one or more semiconductor channel layers. The gate spacer is in contact with a sidewall of the gate metal layer. From a cross-section view, a neck portion of the gate metal layer adjacent to and along the one or more semiconductor channel layers, and one side of the neck portion is retracted by a distance relative to the gate spacer, and the distance is greater than 0 and less than or equal to 2 nanometers.Type: ApplicationFiled: August 28, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Ting Pan, Kuo-Cheng Chiang, Chih-Hao Wang
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Patent number: 11916072Abstract: A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.Type: GrantFiled: July 22, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jia-Chuan You, Chia-Hao Chang, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11916125Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.Type: GrantFiled: July 22, 2022Date of Patent: February 27, 2024Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
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Publication number: 20230155497Abstract: The present invention relates to an AC/DC power conversion module and a method of driving the same. When an AC/DC converter is electrically coupled to an external power source, a microprocessor is electrically energized by a buck auxiliary circuit, under control of the microprocessor, a DC/DC converter is activated for a certain time period, and then, the AC/DC converter is activated. Thereafter, an output voltage of the AC/DC converter is boosted, and an output voltage of the DC/DC converter is boosted accordingly. Power elements in the downstream side DC/DC converter are activated first, and then power elements in the upstream side AC/DC converter are activated, thereby an inrush current is suppressed. Once the external power source is connected, the buck auxiliary circuit will automatically reduce a voltage of the power input to activate the module. It realizes that the module will autonomously operate after being electrically energized.Type: ApplicationFiled: October 27, 2022Publication date: May 18, 2023Inventors: Chen Yuan WU, Chih Hsien WANG, Kuo Cheng WANG, Cheng Chung LEE
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Patent number: 11270000Abstract: A cybersecurity server receives an executable file that has bytecode and metadata of the bytecode. Strings are extracted from the metadata, sorted, and merged into data streams. The data streams are merged to form a combined data stream. A digest of the combined data stream is calculated using a fuzzy hashing algorithm. The similarity of the digest to another digest is determined to detect whether or not the executable file is malware or a member of a malware family.Type: GrantFiled: November 7, 2019Date of Patent: March 8, 2022Assignee: Trend Micro IncorporatedInventors: Chia-Ming Chiang, Po-Han Hao, Kuo-Cheng Wang
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Patent number: 11068595Abstract: A cybersecurity server receives an executable file. The executable file is disassembled to generate assembly code of the executable file. High-entropy blocks and blocks of printable American Standard Code for Information Interchange (ASCII) characters are removed from the assembly code. Instructions of the assembly code are normalized, chunked, and merged into a data stream. The digest of the data stream is calculated using a fuzzy hashing algorithm. The similarity of the digest to a malicious digest is determined to evaluate the executable file for malware.Type: GrantFiled: November 4, 2019Date of Patent: July 20, 2021Assignee: Trend Micro IncorporatedInventors: Chia-Ming Chiang, Po-Han Hao, Kuo-Cheng Wang
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Patent number: 7118397Abstract: A memory card connector includes an insulating housing, a cover engaging with the insulating housing, a plurality of terminals fixed on the insulating housing and an ejection mechanism. The insulating housing has a base plate and a side wall. The base plate has a stopper which extends upward near to the side wall. The ejection mechanism has a slider and a spring. One end of the slider leans against the stopper detachably, and the other end leans against the spring. The spring is compressed between the insulating housing and the slider. Furthermore, a first tilt-preventing portion is provided at the end of the slider which leans against the spring. A corresponding second tilt-preventing portion is provided in the side wall of the insulating housing for engaging with the first tilt-preventing portion to prevent the slider from tilting.Type: GrantFiled: December 19, 2005Date of Patent: October 10, 2006Assignee: Cheng Uei Precision Industry Co., Ltd.Inventors: Yu-Hung Su, Kuo Cheng Wang