Abstract: A method includes forming silicon waveguide sections in a first oxide layer over a substrate, the first oxide layer disposed on the substrate, forming a routing structure over the first oxide layer, the routing structure including one or more insulating layers and one or more conductive features in the one or more insulating layers, recessing regions of the routing structure, forming nitride waveguide sections in the recessed regions of the routing structure, wherein the nitride waveguide sections extend over the silicon waveguide sections, forming a second oxide layer over the nitride waveguide sections, and attaching semiconductor dies to the routing structure, the dies electrically connected to the conductive features.

Abstract: A computing device for providing distributed playback of 360-degree video in a plurality of viewing windows receives a 360-degree video bitstream. The computing device receives a field of view angle for a main viewing window from a user. A user interface comprising the main viewing window and the plurality of peripheral viewing windows is generated, where the plurality of peripheral viewing windows each have a corresponding field of view angle. The computing device executes distributed playback of the 360-degree video in the main viewing window and the plurality of peripheral viewing windows based on the field of view angles of the main viewing window and the plurality of peripheral viewing windows.

Abstract: Field effect transistor and manufacturing method thereof are disclosed. Field effect transistor includes a substrate, a fin, spacers, a gate structure, a hard mask pattern, an insulating layer, and a gate contact. The fin protrudes from the substrate and extends in a first direction. The spacers run in parallel over the fin and extending in a second direction perpendicular to the first direction. The gate structure extends between the spacers and covers the fin. The hard mask pattern covers the gate structure and extends in between the spacers. The insulating layer is disposed over the substrate and covers the hard mask pattern, the gate structure and the spacers. The gate contact penetrates the insulating layer and physically contacts the gate structure. A bottom surface of the gate contact is coplanar with top surfaces of the spacers and the hard mask pattern.

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

Abstract: FinFET devices with source/drain contacts with reduced resistance/capacitance power loss and with an enhanced processing window between the source/drain contacts and a gate via and methods of manufacture are described herein. A metal riser may be formed in a first recess of a source/drain contact of a first material. The metal riser and a contact via may be formed from a second material and the contact via may be formed over the metal riser to provide a hybrid source/drain contact of a finFET with a wide surface contact area at an interface between the source/drain contact and the metal riser. A dielectric fill material and/or a conformal contact etch stop layer may be used to form an isolation region in a second recess of the source/drain contact to extend a processing window disposed between the isolation region and a gate contact of the finFET.

Abstract: Methods of fabricating an integrated circuit device are provided. The integrated circuit device includes a transistor formed on a substrate. The transistor includes a source region, a drain region, and a gate structure between the source region and the drain region. The integrated circuit device also includes a first dielectric layer over the transistor and a first via contact partially in the first dielectric layer and electrically connected to the source region. The integrated circuit device further includes a second via contact partially in the first dielectric layer and electrically connected to the gate structure. In addition, the upper portion of the first via contact and the upper portion of the second via contact protrude from the first dielectric layer.

Abstract: The invention introduces a method for preventing or detecting computer attacks in a cloud-based environment, performed by a processing unit of an apparatus, which contains at least the following steps. A first IP (Internet Protocol) packet is received from a client system through the Internet. A service request is acquired from the first IP packet, which requests service to a protected computer asset. It is determined whether the service request contains a computer attack. An attack prevention/detection operation is performed to prevent an attack from damaging the protected computer asset when the service request contains a computer attack.

Abstract: A first electric stator surrounds a first electric rotor and is configured to cause the first electric rotor to rotate or generate electricity in the first electric stator when the first electric rotor rotates. The first electric stator includes a first set of electric windings. A second electric stator surrounds the second electric rotor and is configured to cause the second electric rotor to rotate or generate electricity in the second electric stator when the second electric rotor rotates. The second electric stator includes a second set of electric windings. The second electric stator is electrically coupled to the first electric stator. A controller is electrically coupled to both the first electric stator and the second electric stator. The controller is configured to exchange an electric current with a combination of the first electric stator and the second electric stator.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure laterally adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering the upper surface of the gate stack, a second insulating capping feature covering the upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from the material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.

Abstract: A video processing system includes an input port and a video processing circuit. The input port obtains device information of a display panel. The video processing circuit obtains an input frame and the device information, configures an image enhancement operation according to the device information, generates an output frame by performing the image enhancement operation upon the input frame, and transmits the output frame to the display panel for video playback.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an insulating layer over a substrate, a gate stack formed in the insulating layer, and an insulating capping layer formed in the insulating layer to cover the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack. The source/drain contact structure has a sidewall that is in direct contact with a sidewall of the insulating capping layer, and an upper surface that is substantially level with an upper surface of the insulating capping layer and an upper surface of the insulating layer. In addition, the semiconductor device structure includes a first via structure above and electrically connected to the gate stack and a second via structure above and electrically connected to the source/drain contact structure.

Abstract: A system includes a retrievable string for use in a completion string of a well, the completion string including an electrical stator. The retrievable string is to be disposed in the completion string, the retrievable string including a rotor for receipt within the electrical stator and to rotate in response to electromagnetic fields generated by the stator, an impeller coupled to the rotor, a housing to surround the impeller, and a recirculation isolator coupled to the housing. The recirculation isolator includes a sealing element and a locking tool, where the sealing element sealingly engages with the completion string, and the locking tool positions the retrievable string in the completion string and detachably couples the retrievable string to the completion string. The locking tool includes a rotational locking feature to engage an indexing receptacle of the completion string.