Patents by Inventor Kuo-Chih Lai

Kuo-Chih Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210295787
    Abstract: The present disclosure relates to a display device including a backlight circuit, a processing circuit, and a clock generation circuit. The backlight circuit is configured to be driven in response to a control signal. The processing circuit is electrically connected to the backlight circuit and is configured to generate a voltage signal and the control signal. The clock generating circuit is electrically connected to the processing circuit to receive the voltage signal. The processing circuit is configured to adjust the control signal according to a clock frequency of the clock signal.
    Type: Application
    Filed: December 9, 2020
    Publication date: September 23, 2021
    Inventors: Sin-Jie WANG, Kuo-Hsiang CHEN, Hsiang-Chi CHENG, Ya-Ting LIN, Shyh-Bin KUO, Yi-Cheng LAI, Yu-Chih WANG, Chung-Hung CHEN
  • Publication number: 20210057643
    Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.
    Type: Application
    Filed: September 20, 2019
    Publication date: February 25, 2021
    Inventors: Shih-Min Chou, Kuo-Chih Lai, Wei-Ming Hsiao, Hui-Ting Lin, Szu-Yao Yu, Nien-Ting Ho, Hsin-Fu Huang, Chin-Fu Lin
  • Publication number: 20200403144
    Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.
    Type: Application
    Filed: July 9, 2019
    Publication date: December 24, 2020
    Inventors: Kuo-Chih Lai, Yi-Syun Chou, Ko-Wei Lin, Pei-Hsun Kao, Wei Chen, Chia-Fu Cheng, Chun-Yao Yang, Chia-Chang Hsu
  • Patent number: 10756128
    Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: August 25, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Shih-Min Chou, Ko-Wei Lin, Chin-Fu Lin, Wei-Chuan Tsai, Chun-Yao Yang, Chia-Fu Cheng, Yi-Syun Chou, Wei Chen
  • Publication number: 20200212090
    Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 2, 2020
    Inventors: Kuo-Chih Lai, Shih-Min Chou, Ko-Wei Lin, Chin-Fu Lin, Wei-Chuan Tsai, Chun-Yao Yang, Chia-Fu Cheng, Yi-Syun Chou, Wei Chen
  • Publication number: 20200006514
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.
    Type: Application
    Filed: September 4, 2019
    Publication date: January 2, 2020
    Inventors: Kuo-Chih Lai, Yun-Tzu Chang, Wei-Ming Hsiao, Nien-Ting Ho, Shih-Min Chou, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Kuan-Chun Lin, Chi-Mao Hsu
  • Patent number: 10490643
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: November 26, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Yun-Tzu Chang, Wei-Ming Hsiao, Nien-Ting Ho, Shih-Min Chou, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Kuan-Chun Lin, Chi-Mao Hsu
  • Patent number: 10340350
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: July 2, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Min Chou, Yun-Tzu Chang, Wei-Ning Chen, Wei-Ming Hsiao, Chia-Chang Hsu, Kuo-Chih Lai, Yang-Ju Lu, Yen-Chen Chen, Chun-Yao Yang
  • Patent number: 10290710
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: May 14, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Ming-Chang Lu, Wei Chen, Hui-Lin Wang, Yi-Ting Liao, Chin-Fu Lin
  • Publication number: 20190074357
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.
    Type: Application
    Filed: September 5, 2017
    Publication date: March 7, 2019
    Inventors: Kuo-Chih Lai, Ming-Chang Lu, Wei Chen, Hui-Lin Wang, Yi-Ting Liao, Chin-Fu Lin
  • Publication number: 20180331193
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.
    Type: Application
    Filed: July 25, 2018
    Publication date: November 15, 2018
    Inventors: Shih-Min Chou, Yun-Tzu Chang, Wei-Ning Chen, Wei-Ming Hsiao, Chia-Chang Hsu, Kuo-Chih Lai, Yang-Ju Lu, Yen-Chen Chen, Chun-Yao Yang
  • Publication number: 20180261675
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.
    Type: Application
    Filed: March 8, 2017
    Publication date: September 13, 2018
    Inventors: Shih-Min Chou, Yun-Tzu Chang, Wei-Ning Chen, Wei-Ming Hsiao, Chia-Chang Hsu, Kuo-Chih Lai, Yang-Ju Lu, Yen-Chen Chen, Chun-Yao Yang
  • Patent number: 10074725
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: September 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Min Chou, Yun-Tzu Chang, Wei-Ning Chen, Wei-Ming Hsiao, Chia-Chang Hsu, Kuo-Chih Lai, Yang-Ju Lu, Yen-Chen Chen, Chun-Yao Yang
  • Patent number: 10068797
    Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: September 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Shu Min Huang, Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
  • Patent number: 9985110
    Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: May 29, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia-Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Min-Chuan Tsai, Kuo-Chin Hung, Wei-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
  • Patent number: 9966425
    Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 8, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jen-Po Huang, Chin-Fu Lin, Bin-Siang Tsai, Xu Yang Shen, Seng Wah Liau, Yen-Chen Chen, Ko-Wei Lin, Chun-Ling Lin, Kuo-Chih Lai, Ai-Sen Liu, Chun-Yuan Wu, Yang-Ju Lu
  • Publication number: 20170323950
    Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.
    Type: Application
    Filed: July 21, 2017
    Publication date: November 9, 2017
    Applicant: United Microelectronics Corp.
    Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia-Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Min-Chuan Tsai, Kuo-Chin Hung, Wei-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
  • Patent number: 9755047
    Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: September 5, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia-Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Min-Chuan Tsai, Kuo-Chin Hung, Wei-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
  • Publication number: 20170236747
    Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.
    Type: Application
    Filed: May 3, 2017
    Publication date: August 17, 2017
    Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Shu Min Huang, Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
  • Patent number: 9728467
    Abstract: A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: August 8, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Yun-Tzu Chang, Shih-Min Chou, Kuo-Chih Lai, Ching-Yun Chang, Hsiang-Chieh Yen, Yen-Chen Chen, Yang-Ju Lu, Nien-Ting Ho, Chi-Mao Hsu