Patents by Inventor Kuo-Chih Lai

Kuo-Chih Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090191714
    Abstract: The present invention provides a method of removing oxides. First, a substrate having the oxides is loaded into a reaction chamber, which includes a susceptor setting in the bottom portion of the chamber, a shower head setting above the susceptor, and a heater setting above the susceptor. Subsequently, an etching process is performed. A first thermal treatment process is then carried out. Finally, a second thermal treatment process is carried out, and a reaction temperature of the second thermal treatment process is higher than a reaction temperature of the first thermal treatment process.
    Type: Application
    Filed: January 24, 2008
    Publication date: July 30, 2009
    Inventors: Kuo-Chih Lai, Yi-Wei Chen, Nien-Ting Ho, Teng-Chun Tsai
  • Publication number: 20090155999
    Abstract: A method for fabricating a metal silicide film is described. After providing a silicon material layer, a metal alloy layer is formed to cover the silicon material layer. A thermal process is performed to form a metal alloy silicide layer in a self-aligned way. A wet etching process is performed by using a cleaning solution including sulfuric acid and hydrogen peroxide to remove the residual metals and unreacted metal alloy.
    Type: Application
    Filed: December 13, 2007
    Publication date: June 18, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Wei Chen, Kuo-Chih Lai, Nien-Ting Ho
  • Publication number: 20090090395
    Abstract: A method of removing particles from a wafer is provided. The method is adopted after a process for removing unreactive metal of a salicide process or after a salicide process and having oxide residue remaining on a wafer or after a chemical vapor deposition (CVD) process that resulted with particles on a wafer. The method includes performing at least two cycles (stages) of intermediate rinse process. Each cycle of the intermediate rinse process includes conducting a procedure of rotating the wafer at a high speed first, and then conducting a procedure of rotating the wafer at a low speed.
    Type: Application
    Filed: October 3, 2007
    Publication date: April 9, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Wei Chen, Bao-Tzeng Huang, An-Chi Liu, Chao-Ching Hsieh, Nien-Ting Ho, Kuo-Chih Lai
  • Publication number: 20080188088
    Abstract: A method of forming a porous low-k layer is described. A CVD process is conducted to a substrate, wherein a framework precursor and a porogen precursor are supplied. In an end period of the supply of the framework precursor, the value of at least one deposition parameter negatively correlated with the density of the product of the CVD process is decreased.
    Type: Application
    Filed: February 7, 2007
    Publication date: August 7, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Mei-Ling Chen, Kuo-Chih Lai, Su-Jen Sung, Chien-Chung Huang, Yu-Tsung Lai
  • Publication number: 20080166498
    Abstract: A method of curing a porous low-k layer is described, which is applied to a substrate with a porous low-k layer formed thereon, wherein the porous low-k: layer contains a porogen. A first UV-curing treatment is performed to the porous low-k layer under a relatively milder condition, and then a second UV-curing treatment is performed to the porous low-k layer under a relatively harsher condition to finish the curing of the porous low-k layer.
    Type: Application
    Filed: January 10, 2007
    Publication date: July 10, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Mei-Ling Chen, Kuo-Chih Lai, Su-Jen Sung
  • Patent number: 7378343
    Abstract: A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: May 27, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Jei-Ming Chen, Miao-Chun Lin, Kuo-Chih Lai, Mei-Ling Chen, Cheng-Ming Weng, Chun-Jen Huang, Yu-Tsung Lai
  • Publication number: 20080026579
    Abstract: A copper damascene process includes providing a substrate having a dielectric layer thereon, forming at least a copper damascene structure in the dielectric layer, performing a heat treatment on the substrate, and performing a reduction plasma treatment on a surface of the copper damascene structure. The impurities formed in the copper damascene process are removed by the heat treatment, therefore the copper damascene structure is completely reduced by the reduction plasma treatment and is improved.
    Type: Application
    Filed: July 25, 2006
    Publication date: January 31, 2008
    Inventors: Kuo-Chih Lai, Mei-Ling Chen, Jei-Ming Chen, Hsin-Hsing Chen, Shih-Feng Su, Meng-Chi Chen
  • Publication number: 20070218214
    Abstract: A method of improving adhesion property of a dielectric layer is provided. A dielectric layer is formed over a substrate. A plasma surface process comprising a plasma gas containing helium or hydrogen is performed to treat the surface of the dielectric layer. A cap layer is formed on the dielectric layer.
    Type: Application
    Filed: March 14, 2006
    Publication date: September 20, 2007
    Inventors: Kuo-Chih Lai, Mei-Ling Chen, Jei-Ming Chen
  • Publication number: 20070173070
    Abstract: A method for fabricating a porous low-k dielectric film includes providing a substrate, performing a first CVD process by providing a back-bone precursor to form an interface dielectric layer, performing a second CVD process by providing a porogen precursor to form a back-bone layer, and removing the porogens in the back-bone layer so that the back-bone layer becomes an ultra low-k dielectric layer. The interface dielectric layer and the ultra low-k dielectric layer compose a porous low-k dielectric film.
    Type: Application
    Filed: January 26, 2006
    Publication date: July 26, 2007
    Inventors: Mei-Ling Chen, Su-Jen Sung, Kuo-Chih Lai, Jei-Ming Chen
  • Publication number: 20070111514
    Abstract: A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.
    Type: Application
    Filed: November 17, 2005
    Publication date: May 17, 2007
    Inventors: Jei-Ming Chen, Miao-Chun Lin, Kuo-Chih Lai, Mei-Ling Chen, Cheng-Ming Weng, Chun-Jen Huang, Yu-Tsung Lai
  • Publication number: 20070077751
    Abstract: A method of restoring a low-k material is described, applied to a substrate with a low-k material thereon, wherein the substrate has been subject to a previous process that raised the k-value of the low-k material. The method includes performing a plasma treatment to the low-k material to decrease the k-value thereof.
    Type: Application
    Filed: October 3, 2005
    Publication date: April 5, 2007
    Inventors: Mei-Ling Chen, Jei-Ming Chen, Kuo-Chih Lai, Wen-Chieh Su
  • Publication number: 20060281299
    Abstract: A dielectric layer overlying a substrate is prepared. A damascene opening is etched into the dielectric layer. The damascene opening is filled with copper or copper alloy. A surface of the copper or copper alloy is treated with hydrogen-containing plasma such as H2 or NH3 plasma. The treated surface of the copper or copper alloy then reacts with trimethylsilane or tertramethylsilane under plasma enhanced chemical vapor deposition (PECVD) conditions. Subsequently, by PECVD, a silicon carbide layer is in-situ deposited on the copper or copper alloy.
    Type: Application
    Filed: August 3, 2006
    Publication date: December 14, 2006
    Inventors: Jei-Ming Chen, Chin-Hsiang Lin, Chih-Chien Liu, Kuo-Chih Lai
  • Publication number: 20060199367
    Abstract: A manufacturing method of interconnect is provided. A dielectric layer is provided. A metal layer is formed in the dielectric layer. A fluorine-containing barrier layer is formed on the dielectric layer and covers the metal layer. The fluorine-containing barrier layer is formed by using chemical deposition method and introducing fluorine to the film in-situ.
    Type: Application
    Filed: December 7, 2005
    Publication date: September 7, 2006
    Inventors: Jim-Jey Huang, Chih-Chien Liu, Feng-Yu Hsu, Jei-Ming Chen, Kuo-Chih Lai
  • Publication number: 20060040490
    Abstract: A dielectric layer overlying a substrate is prepared. A damascene opening is etched into the dielectric layer. The damascene opening is filled with copper or copper alloy. A surface of the copper or copper alloy is treated with hydrogen-containing plasma such as H2 or NH3 plasma. The treated surface of the copper or copper alloy then reacts with trimethylsilane or tertramethylsilane under plasma enhanced chemical vapor deposition (PECVD) conditions. Subsequently, by PECVD, a silicon carbide layer is in-situ deposited on the copper or copper alloy.
    Type: Application
    Filed: August 18, 2004
    Publication date: February 23, 2006
    Inventors: Jei-Ming Chen, Chin-Hsiang Lin, Chih-Chien Liu, Kuo-Chih Lai
  • Patent number: 6296554
    Abstract: A non-circular workpiece carrier, which includes a wheel-like carrier body, and at least one carriage, wherein the wheel-like carrier body has a transmission unit disposed around the periphery thereof, which receives a transmission power for causing the wheel-like carrier body to turn round, and at least one carrier unit; the at least one carriage is respectively disposed in the at least one carrier unit to hold non-circular workpiece, and forced to gyrate in the at least one carrier unit relative to the wheel-like carrier body, enabling loaded non-circular workpiece to be surface-processed (ground, polished, etc.) more evenly. Different carriages are alternatively used with the carrier body subject to the shapes of workpiece to be processed.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: October 2, 2001
    Assignees: Industrial Technology Research Institute, Kinik Precision Grinding Co.
    Inventors: Kuo-Chih Lai, Chang-Ku Hung