Patents by Inventor Kuo-Chin Chang

Kuo-Chin Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11145564
    Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method for integrated circuit (IC) fabrication includes forming a passivation layer over a first contact feature, forming a second contact feature over and through the passivation layer to electrically connect to the first contact feature, and forming a multi-layer passivation structure over the second contact feature and over the passivation layer. Forming the multi-layer passivation structure includes depositing a first nitride layer, an oxide layer over the first nitride layer, and a second nitride layer over the oxide layer.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 11127704
    Abstract: A semiconductor device includes a substrate and at least one bump structure disposed over the substrate. The at least one bump structure includes a pillar formed of a metal having a lower solderability than copper or a copper alloy to a solder alloy disposed over the substrate. A solder alloy is formed directly over and in contact with an upper surface of the metal having the lower solderability than copper or a copper alloy. The pillar has a height of greater than 10 ?m.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Haw Tsao, Chen-Shien Chen, Cheng-Hung Tsai, Kuo-Chin Chang, Li-Huan Chu
  • Publication number: 20210259409
    Abstract: A structure of reduced profile to render crushproof a cabinet with the structure can be installed in an opening of the cabinet. The structure includes a first frame and a reinforcing portion. Two ends of the reinforcing portion are both connected to the first frame, so that the reinforcing portion is received in the first frame. The crush-proofing structure is movably connected to the opening of the cabinet.
    Type: Application
    Filed: March 11, 2020
    Publication date: August 26, 2021
    Inventors: HSUEH-CHIN LU, KUO-CHIH HUNG, CHIH-FENG CHANG, HAO-WEN CHENG
  • Publication number: 20210233883
    Abstract: A method of forming a semiconductor structure is provided. A layout of a substrate is provided. The layout includes a surface having an inner region and an outer region surrounding the inner region. An under bump metallurgy (UBM) pad region within the outer region is defined. The UBM pad region is partitioned into a first zone and a second zone, wherein the first zone faces towards a center of the substrate, and the second zone faces away from the center of the substrate. The substrate is provided according to the layout, wherein the providing of the substrate includes forming a conductive via in the substrate. The conductive via is disposed outside the second zone and at least partially overlaps the first zone from a top view perspective. A UBM pad is formed over the conductive via and within the UBM pad region.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Inventors: KUO-CHIN CHANG, YEN-KUN LAI, KUO-CHING HSU, MIRNG-JI LII
  • Patent number: 11018099
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a semiconductor chip; a substrate facing an active surface of the semiconductor chip; and a conductive bump extending from the active surface of the semiconductor chip toward the substrate, wherein the conductive bump comprises: a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment comprises the same segment height in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment comprises a volume defined by the multiplication of the segment height with the average cross-sectional area of the bump segment; wherein the ratio of the total volume of the first group of bump segments to the total volume of the second group of bump segments is between about 0.03 and about 0.8.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pei-Haw Tsao, An-Tai Xu, Huang-Ting Hsiao, Kuo-Chin Chang
  • Publication number: 20210118767
    Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip over a substrate. The method includes forming a heat-spreading wall structure over the substrate. The heat-spreading wall structure is adjacent to the chip, and there is a first gap between the chip and the heat-spreading wall structure. The method includes forming a first heat conductive layer in the first gap. The method includes forming a second heat conductive layer over the chip. The method includes disposing a heat-spreading lid over the substrate to cover the heat-spreading wall structure, the first heat conductive layer, the second heat conductive layer, and the chip. The heat-spreading lid is bonded to the substrate, the heat-spreading wall structure, the first heat conductive layer, and the second heat conductive layer.
    Type: Application
    Filed: October 16, 2019
    Publication date: April 22, 2021
    Inventors: Shin CHI, Chien-Hao HSU, Kuo-Chin CHANG, Cheng-Nan LIN, Mirng-Ji LII
  • Patent number: 10985124
    Abstract: A semiconductor structure includes a substrate having a surface and a conductive via in the substrate. The surface has an inner region and an outer region surrounding the inner region. The semiconductor structure also includes an under bump metallurgy (UBM) pad on the surface and within the outer region, where the UBM pad has a first zone and a second zone. The first zone faces towards a center of the surface and the second zone faces away from the center of the surface. The conductive via is disposed outside the second zone and at least partially overlaps the first zone from a top view perspective.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuo-Chin Chang, Yen-Kun Lai, Kuo-Ching Hsu, Mirng-Ji Lii
  • Publication number: 20210091029
    Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 10861810
    Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20200168574
    Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.
    Type: Application
    Filed: April 23, 2019
    Publication date: May 28, 2020
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20200105634
    Abstract: The present disclosure provides a method that includes providing an integrated circuit (IC) substrate having various devices and an interconnection structure that couples the devices to an integrated circuit; forming a first passivation layer on the IC substrate; forming a redistribution layer on the first passivation layer, the redistribution layer being electrically connected to the interconnection structure; forming a second passivation layer on the redistribution layer and the first passivation layer; forming a polyimide layer on the second passivation layer; patterning the polyimide layer, resulting in a polyimide opening in the polyimide layer; and etching the second passivation layer through the polyimide opening using the polyimide layer as an etch mask.
    Type: Application
    Filed: May 14, 2019
    Publication date: April 2, 2020
    Inventors: Chih-Fan Huang, Mao-Nan Wang, Kuo-Chin Chang, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20200058589
    Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a redistribution layer over the substrate. The chip structure includes a bonding pad over the redistribution layer. The chip structure includes a shielding pad over the redistribution layer and surrounding the bonding pad. The chip structure includes an insulating layer over the redistribution layer and the shielding pad. The chip structure includes a bump over the bonding pad and the insulating layer. A sidewall of the bump is over the shielding pad.
    Type: Application
    Filed: May 25, 2019
    Publication date: February 20, 2020
    Inventors: Hong-Seng SHUE, Sheng-Han TSAI, Kuo-Chin CHANG, Mirng-Ji LII, Kuo-Ching HSU
  • Publication number: 20200006183
    Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method for integrated circuit (IC) fabrication includes forming a passivation layer over a first contact feature, forming a second contact feature over and through the passivation layer to electrically connect to the first contact feature, and forming a multi-layer passivation structure over the second contact feature and over the passivation layer. Forming the multi-layer passivation structure includes depositing a first nitride layer, an oxide layer over the first nitride layer, and a second nitride layer over the oxide layer.
    Type: Application
    Filed: April 26, 2019
    Publication date: January 2, 2020
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20190326244
    Abstract: A semiconductor structure includes a substrate having a surface and a conductive via in the substrate. The surface has an inner region and an outer region surrounding the inner region. The semiconductor structure also includes an under bump metallurgy (UBM) pad on the surface and within the outer region, where the UBM pad has a first zone and a second zone. The first zone faces towards a center of the surface and the second zone faces away from the center of the surface. The conductive via is disposed outside the second zone and at least partially overlaps the first zone from a top view perspective.
    Type: Application
    Filed: April 23, 2018
    Publication date: October 24, 2019
    Inventors: KUO-CHIN CHANG, YEN-KUN LAI, KUO-CHING HSU, MIRNG-JI LII
  • Publication number: 20190164920
    Abstract: A semiconductor device includes a substrate and at least one bump structure disposed over the substrate. The at least one bump structure includes a pillar formed of a metal having a lower solderability than copper or a copper alloy to a solder alloy disposed over the substrate. A solder alloy is formed directly over and in contact with an upper surface of the metal having the lower solderability than copper or a copper alloy. The pillar has a height of greater than 10 ?m.
    Type: Application
    Filed: October 24, 2018
    Publication date: May 30, 2019
    Inventors: Pei-Haw TSAO, Chen-Shien CHEN, Cheng-Hung TSAI, Kuo-Chin CHANG, Li-Huan CHU
  • Publication number: 20190096832
    Abstract: A method for fabricating a semiconductor structure is provided. The method includes: providing a semiconductor chip comprising an active surface; forming a conductive bump over the active surface of the semiconductor chip; and coupling the conductive bump to a substrate. The conductive bump includes a plurality of bump segments including a first group of bump segments and a second group of bump segments. Each bump segment has a same segment thickness in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment has a volume defined by a multiplication of the same segment thickness with an average cross-sectional area of the bump segment in a plane parallel to the active surface of the semiconductor chip. A ratio of a total volume of the first group of bump segments to a total volume of the second group of bump segments is between 0.03 and 0.8.
    Type: Application
    Filed: November 30, 2018
    Publication date: March 28, 2019
    Inventors: PEI-HAW TSAO, AN-TAI XU, HUANG-TING HSIAO, KUO-CHIN CHANG
  • Patent number: 10157831
    Abstract: A semiconductor device includes a substrate and a contact pad over the substrate. The semiconductor device further includes a conductive via electrically connected to the contact pad. The conductive via includes a conductive via layer having a first thickness, and a first conductive layer, wherein the first conductive layer is between the contact pad and the conductive via layer. The semiconductor device further includes a conductive pillar electrically connected to the conductive via. The conductive pillar includes a conductive pillar layer having a second thickness, and a second conductive layer having outer edges substantially aligned with outer edges of the conductive pillar layer, wherein the second conductive layer is between the conductive via layer and the conductive pillar layer. A ratio of the first thickness to the second thickness ranges from about 0.33 to about 0.55.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Chin Chang, Yuh Chern Shieh
  • Publication number: 20170062329
    Abstract: A semiconductor device includes a substrate and a contact pad over the substrate. The semiconductor device further includes a conductive via electrically connected to the contact pad. The conductive via includes a conductive via layer having a first thickness, and a first conductive layer, wherein the first conductive layer is between the contact pad and the conductive via layer. The semiconductor device further includes a conductive pillar electrically connected to the conductive via. The conductive pillar includes a conductive pillar layer having a second thickness, and a second conductive layer having outer edges substantially aligned with outer edges of the conductive pillar layer, wherein the second conductive layer is between the conductive via layer and the conductive pillar layer. A ratio of the first thickness to the second thickness ranges from about 0.33 to about 0.55.
    Type: Application
    Filed: November 15, 2016
    Publication date: March 2, 2017
    Inventors: Kuo-Chin CHANG, Yuh Chern SHIEH
  • Patent number: 9514978
    Abstract: A method for fabricating a semiconductor device includes forming a first photo-sensitive layer over a contact pad, wherein the contact pad is on a substrate. The method further includes patterning the first photo-sensitive layer to form a first opening over a portion of the contact pad. The method further includes plating a conductive via in the first opening; and removing the first photo-sensitive layer. The method further includes forming a passivation layer over the substrate, contact pad, and conductive via, and exposing the conductive via by grinding the passivation layer. The method further includes forming a second photo-sensitive layer over the conductive via and passivation layer. The method further includes patterning the second photo-sensitive layer to form a second opening larger than and completely exposing the conductive via. The method further includes plating a conductive pillar in the second opening; and removing the second photo-sensitive layer.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: December 6, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Chin Chang, Yuh Chern Shieh
  • Publication number: 20160148891
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a semiconductor chip; a substrate facing an active surface of the semiconductor chip; and a conductive bump extending from the active surface of the semiconductor chip toward the substrate, wherein the conductive bump comprises: a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment comprises the same segment height in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment comprises a volume defined by the multiplication of the segment height with the average cross-sectional area of the bump segment; wherein the ratio of the total volume of the first group of bump segments to the total volume of the second group of bump segments is between about 0.03 and about 0.8.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 26, 2016
    Inventors: PEI-HAW TSAO, AN-TAI XU, HUANG-TING HSIAO, KUO-CHIN CHANG