Patents by Inventor Kuo-Chin Chang

Kuo-Chin Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7804177
    Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 ?m. A plurality of through-hole vias are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: September 28, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu Wei Lu, Clinton Chao, Ann Luh, Tjandra Winata Karta, Jerry Tzou, Kuo-Chin Chang
  • Patent number: 7662665
    Abstract: A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: February 16, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Shien Chen, Kuo-Chin Chang, Szu-Wei Lu, Pei-Haw Tsao, Chung-Yu Wang, Han-Liang Tseng, Mirng-Ji Lii
  • Publication number: 20090130840
    Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.
    Type: Application
    Filed: November 16, 2007
    Publication date: May 21, 2009
    Inventors: Chung Yu Wang, Chien-Hsiun Lee, Pei-Haw Tsao, Kuo-Chin Chang, Chung-Yi Lin, Bill Kiang
  • Publication number: 20080296764
    Abstract: An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint.
    Type: Application
    Filed: May 29, 2007
    Publication date: December 4, 2008
    Inventors: Kuo-Chin Chang, Han-Ping Pu, Pei-Haw Tsao
  • Publication number: 20080174002
    Abstract: A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate.
    Type: Application
    Filed: January 22, 2007
    Publication date: July 24, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Shien Chen, Kuo-Chin Chang, Szu-Wei Lu, Pei-Haw Tsao, Chung-Yu Wang, Han-Liang Tseng, Mirng-Ji Lii
  • Publication number: 20080023850
    Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 ?m. A plurality of through-hole vias are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Inventors: Szu Wei Lu, Clinton Chao, Ann Luh, Tjandra Winata Karta, Jerry Tzou, Kuo-Chin Chang
  • Publication number: 20070246821
    Abstract: A semiconductor package assembly having reduced stresses and a method for forming the same are provided. The method includes providing a package substrate comprising a base material, forming an interconnect structure overlying the package substrate, attaching at least one chip to a first surface of the package substrate, thinning the package substrate from a second surface opposite the first surface wherein the semiconductor material is substantially removed, and attaching ball grid array (BGA) balls to deep vias exposed on the second surface of the package substrate after thinning the package substrate.
    Type: Application
    Filed: April 20, 2006
    Publication date: October 25, 2007
    Inventors: Szu Lu, Clinton Chao, Tjandra Karta, Jerry Tzou, Kuo-Chin Chang
  • Patent number: 7271480
    Abstract: A constraint stiffener for reinforcing an integrated circuit package is provided. In one embodiment, the constraint stiffener comprises a rigid, planar base element for bonding to an integrated circuit substrate. The base element has a plurality of elongated support members, and the base element has an opening therein for surrounding an integrated circuit. The base element and support members reduce warpage due to thermal expansion mismatches between at least the integrated circuit and the substrate. In one embodiment, the elongated support members are detachable from the corners of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the corners of the base element. In yet another embodiment, the elongated support members are detachable from about the midsections of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the midsections of the base element.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: September 18, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chin Chang, Ching-Yu Ni
  • Publication number: 20070069366
    Abstract: A constraint stiffener for reinforcing an integrated circuit package is provided. In one embodiment, the constraint stiffener comprises a rigid, planar base element for bonding to an integrated circuit substrate. The base element has a plurality of elongated support members, and the base element has an opening therein for surrounding an integrated circuit. The base element and support members reduce warpage due to thermal expansion mismatches between at least the integrated circuit and the substrate. In one embodiment, the elongated support members are detachable from the corners of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the corners of the base element. In yet another embodiment, the elongated support members are detachable from about the midsections of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the midsections of the base element.
    Type: Application
    Filed: September 29, 2005
    Publication date: March 29, 2007
    Inventors: Kuo-Chin Chang, Ching-Yu Ni
  • Publication number: 20060180944
    Abstract: A flip chip ball grid array package is provided. In one embodiment, a flip chip ball grid array package comprises a substrate having an upper surface and a lower surface opposite the upper surface and a microelectronic element comprising a set of solder balls being secured to the upper surface of the substrate. A constraint member is secured to the lower surface of the substrate so that the constraint member has a degree of rigidity to reduce warpage due to thermal expansion mismatches between at least the microelectronic element and the substrate.
    Type: Application
    Filed: April 10, 2006
    Publication date: August 17, 2006
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chin Chang, Simon Lu
  • Publication number: 20060055032
    Abstract: A semiconductor assembly has solder bumps with increased reliability. One embodiment of an assembly comprises a first substrate having at least one conductive pad on its surface; a second substrate having at least one conductive pad on its surface; at least one conductive stud; and at least one solder bump in contact with the conductive pad on the first substrate, and in contact with the conductive pad of the second substrate, and formed around the at least one conductive stud. Methods for providing these assemblies are included.
    Type: Application
    Filed: September 14, 2004
    Publication date: March 16, 2006
    Inventors: Kuo-Chin Chang, Kuo-Ning Chiang
  • Publication number: 20060043602
    Abstract: A flip chip ball grid array package is provided. In one embodiment, a flip chip ball grid array package comprises a substrate having an upper surface and a lower surface opposite the upper surface and a microelectronic element comprising a set of solder balls being secured to the upper surface of the substrate. A constraint member is secured to the lower surface of the substrate so that the constraint member has a degree of rigidity to reduce warpage due to thermal expansion mismatches between at least the microelectronic element and the substrate.
    Type: Application
    Filed: September 2, 2004
    Publication date: March 2, 2006
    Inventors: Kuo-Chin Chang, Simon Lu
  • Publication number: 20050228740
    Abstract: A machine purchasing system includes a database server (1), an application server (2), and a plurality of distributed client computers (4). The system receives historical transaction records from a financial management system (6) and current prices from an electronic marketing system (5), and sets a base price for each to-be-purchased machine based on the above received information. Users select one or more eligible suppliers based on the base price and the supplier's information. The client computers are for searching information stored in the database server. A related machine purchasing method is also disclosed.
    Type: Application
    Filed: April 9, 2004
    Publication date: October 13, 2005
    Inventors: Kuo-Chin Chang, Wu Ma, Junma Zheng
  • Publication number: 20040193533
    Abstract: A project bidding transaction management system in accordance with a preferred embodiment of the present invention includes a database server (1) for storing data used or generated in implementing the project bidding transaction management system, and an application server (2) for managing project bidding transactions. The application server includes: a basic data maintenance module (20) for receiving requirements of outsourcing projects, and generating specifications for the outsourcing projects; a bidder selection module (21) for selecting a plurality of suitable bidders from a list of companies wishing to bid on an outsourcing project; a price negotiation management module (22) for performing price negotiations with bidders, and generating price negotiation records; and a bid comparison module (23) for determining a winning bidder as a contractor for each outsourcing project, and generating bid results. A project bidding transaction management method is also disclosed in the present invention.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 30, 2004
    Inventors: Kuo-Chin Chang, Wu Ma, J. Junma Zheng
  • Publication number: 20040044679
    Abstract: A system and method for generating reports from a website program residing in a web server (30). The system comprises: a data collection module (41) that periodically gathers data to update a database (51); a user interface module (42) that manages users' requests, said user requests including requests for logon and requests for reports; a data service module (43) that retrieves from the database data requested for generation of reports; and a report generation module (44) that encapsulates instances of requests for reports and instantiates said instances to generate reports based on data supplied by the data service module in accordance with requests for reports. Users can access the system through web browsers to request required reports. One example of such reports is reports containing financial data.
    Type: Application
    Filed: December 27, 2002
    Publication date: March 4, 2004
    Inventors: Kuo-Chin Chang, WenZhen Ma, Nong Ji, Chia-Chi Huang