Patents by Inventor Kuo-Chin Chang
Kuo-Chin Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20160148891Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a semiconductor chip; a substrate facing an active surface of the semiconductor chip; and a conductive bump extending from the active surface of the semiconductor chip toward the substrate, wherein the conductive bump comprises: a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment comprises the same segment height in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment comprises a volume defined by the multiplication of the segment height with the average cross-sectional area of the bump segment; wherein the ratio of the total volume of the first group of bump segments to the total volume of the second group of bump segments is between about 0.03 and about 0.8.Type: ApplicationFiled: November 26, 2014Publication date: May 26, 2016Inventors: PEI-HAW TSAO, AN-TAI XU, HUANG-TING HSIAO, KUO-CHIN CHANG
-
Publication number: 20160005645Abstract: A method for fabricating a semiconductor device includes forming a first photo-sensitive layer over a contact pad, wherein the contact pad is on a substrate. The method further includes patterning the first photo-sensitive layer to form a first opening over a portion of the contact pad. The method further includes plating a conductive via in the first opening; and removing the first photo-sensitive layer. The method further includes forming a passivation layer over the substrate, contact pad, and conductive via, and exposing the conductive via by grinding the passivation layer. The method further includes forming a second photo-sensitive layer over the conductive via and passivation layer. The method further includes patterning the second photo-sensitive layer to form a second opening larger than and completely exposing the conductive via. The method further includes plating a conductive pillar in the second opening; and removing the second photo-sensitive layer.Type: ApplicationFiled: September 18, 2015Publication date: January 7, 2016Inventors: Kuo-Chin CHANG, Yuh Chern SHIEH
-
Patent number: 9159638Abstract: The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate and having an opening with a first width over the contact pad; a conductive via within the opening; and a conductive pillar having a second width completely covering the conductive via, wherein a ratio of the first width to the second width is from about 0.15 to 0.55.Type: GrantFiled: May 26, 2011Date of Patent: October 13, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Chin Chang, Yuh Chern Shieh
-
Patent number: 9136211Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.Type: GrantFiled: July 19, 2013Date of Patent: September 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Chien-Hsun Lee, Pei-Haw Tsao, Kuo-Chin Chang, Chung-Yi Lin, Bill Kiang
-
Patent number: 8976529Abstract: In a package structure, a stiffener ring is over and bonded to a top surface of a first package component. A second package component is over and bonded to the top surface of the first package component, and is encircled by the stiffener ring. A metal lid is over and bonded to the stiffener ring. The metal lid has a through-opening.Type: GrantFiled: January 14, 2011Date of Patent: March 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Yi Lin, Po-Yao Lin, Tsung-Shu Lin, Kuo-Chin Chang, Shou-Yi Wang
-
Patent number: 8704383Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 ?m. A plurality of traces is formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.Type: GrantFiled: April 20, 2012Date of Patent: April 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Wei Lu, Clinton Chao, Ann Luh, Tjandra Winata Karta, Jerry Tzou, Kuo-Chin Chang
-
Publication number: 20130299984Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.Type: ApplicationFiled: July 19, 2013Publication date: November 14, 2013Inventors: Chung Yu Wang, Chien-Hsun Lee, Pei-Haw Tsao, Kuo-Chin Chang, Chung-Yi Lin, Bill Kiang
-
Patent number: 8519535Abstract: A method comprises determining a warpage of an integrated circuit (IC) package design. The IC package design includes a substrate having a top solder mask on a first major surface and a bottom solder mask on a second major surface opposite the first major surface. The first major surface has an IC die mounted over the top solder mask. The design is modified, including modifying an average thickness of one of the group consisting of the top solder mask and the bottom solder mask, so as to reduce the warpage. An IC package is fabricated according to the modified design.Type: GrantFiled: May 11, 2011Date of Patent: August 27, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Shu Lin, Yuh Chern Shieh, Kuo-Chin Chang
-
Patent number: 8492263Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.Type: GrantFiled: November 16, 2007Date of Patent: July 23, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Chien-Hsiun Lee, Pei-Haw Tsao, Kuo-Chin Chang, Chung-Yi Lin, Bill Kiang
-
Publication number: 20120306067Abstract: According to an embodiment, an integrated circuit package comprises a chip, a thermal component, and a molding compound. The chip comprises an active surface and a backside surface opposite the active surface. The thermal component is physically coupled to the backside surface of the chip. The molding compound encapsulates the chip, and an exposed surface of the thermal component is exposed through the molding compound. Another embodiment is a method to form an integrated circuit package.Type: ApplicationFiled: June 2, 2011Publication date: December 6, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Haw Tsao, Kuo-Chin Chang, Han-Ping Pu
-
Publication number: 20120299161Abstract: The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate and having an opening with a first width over the contact pad; a conductive via within the opening; and a conductive pillar having a second width completely covering the conductive via, wherein a ratio of the first width to the second width is from about 0.15 to 0.55.Type: ApplicationFiled: May 26, 2011Publication date: November 29, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Chin CHANG, Yuh Chern SHIEH
-
Publication number: 20120286417Abstract: A method comprises determining a warpage of an integrated circuit (IC) package design. The IC package design includes a substrate having a top solder mask on a first major surface and a bottom solder mask on a second major surface opposite the first major surface. The first major surface has an IC die mounted over the top solder mask. The design is modified, including modifying an average thickness of one of the group consisting of the top solder mask and the bottom solder mask, so as to reduce the warpage. An IC package is fabricated according to the modified design.Type: ApplicationFiled: May 11, 2011Publication date: November 15, 2012Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Shu Lin, Yuh Chern Shieh, Kuo-Chin Chang
-
Publication number: 20120199974Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 ?m. A plurality of traces is formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.Type: ApplicationFiled: April 20, 2012Publication date: August 9, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Szu Wei Lu, Clinton Chao, Ann Luh, Tjandra Winata Karta, Jerry Tzou, Kuo-Chin Chang
-
Publication number: 20120182694Abstract: In a package structure, a stiffener ring is over and bonded to a top surface of a first package component. A second package component is over and bonded to the top surface of the first package component, and is encircled by the stiffener ring. A metal lid is over and bonded to the stiffener ring. The metal lid has a through-opening.Type: ApplicationFiled: January 14, 2011Publication date: July 19, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Yi Lin, Po-Yao Lin, Tsung-Shu Lin, Kuo-Chin Chang, Shou-Yi Wang
-
Patent number: 8174129Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 ?m. A plurality of traces are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.Type: GrantFiled: August 10, 2010Date of Patent: May 8, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Szu Wei Lu, Clinton Chao, Ann Luh, Tjandra Winata Karta, Jerry Tzou, Kuo-Chin Chang
-
Patent number: 7932601Abstract: An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint.Type: GrantFiled: October 6, 2010Date of Patent: April 26, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chin Chang, Han-Ping Pu, Pei-Haw Tsao
-
Publication number: 20110057313Abstract: An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint.Type: ApplicationFiled: October 6, 2010Publication date: March 10, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chin Chang, Han-Ping Pu, Pei-Haw Tsao
-
Publication number: 20100301477Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 ?m. A plurality of traces are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.Type: ApplicationFiled: August 10, 2010Publication date: December 2, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu Wei Lu, Clinton Chao, Ann Luh, Tjandra Winata Karta, Jerry Tzou, Kuo-Chin Chang
-
Patent number: 7820543Abstract: An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint.Type: GrantFiled: May 29, 2007Date of Patent: October 26, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chin Chang, Han-Ping Pu, Pei-Haw Tsao
-
Patent number: 7804177Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 ?m. A plurality of through-hole vias are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.Type: GrantFiled: July 26, 2006Date of Patent: September 28, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu Wei Lu, Clinton Chao, Ann Luh, Tjandra Winata Karta, Jerry Tzou, Kuo-Chin Chang