Patents by Inventor Kuo-Ching Hsu

Kuo-Ching Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250118695
    Abstract: A package component includes an insulating substrate, a semiconductor structure, a first conductive line and a conductive pad. The semiconductor structure is disposed in the insulating substrate and separated from the insulating substrate. The first conductive line is disposed on a first side of the insulating substrate. The conductive pad is disposed on a first side of the semiconductor structure. The first conductive line and the conductive pad include a same material. A surface roughness of the conductive pad is greater than a surface roughness of the first conductive line.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Inventors: MING-WEI PENG, HUNG EN HSU, KUO-CHING HSU
  • Publication number: 20250105115
    Abstract: A semiconductor structure includes a conductive bump disposed between a substrate and a board; an isolation member disposed over the board and surrounding the conductive bump and the substrate; a metallic member disposed between the isolation member and the conductive bump; and a solder disposed between the substrate and the board and configured to attach the metallic member to the substrate and the board. A method of manufacturing a semiconductor structure includes disposing a first solder on a first surface of a substrate; disposing a metallic member to the first surface of the substrate by the first solder; disposing a second solder on a board; and bonding the metallic member to the board by the second solder.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Inventors: Chia-Jen Cheng, Kuo-Ching Hsu
  • Publication number: 20250079327
    Abstract: Semiconductor package and method of manufacturing are presented herein. In an embodiment, a device is provided that includes a first semiconductor component embedded in a first core substrate, a first redistribution layer on a first side of the first core substrate, a second redistribution layer on a second side of the first core substrate opposite the first side, a first resin film over the second redistribution layer, a second semiconductor component embedded in a second core substrate, a third redistribution layer on a third side of the second core substrate, wherein the third redistribution layer is bonded to the second redistribution layer by the first resin film, a fourth redistribution layer on a fourth side of the second core substrate opposite the third side, and a through hole via extending through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, and the fourth redistribution layer.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 6, 2025
    Inventors: Yu-Huan Chen, Kai-Yi Tang, Kuo-Ching Hsu
  • Publication number: 20250079242
    Abstract: Methods and pad structures to test via accuracy are provided. A method according to the present disclosure includes forming a first pad and a second pad on a device component, wherein the second pad includes a via landing area and a clearance opening, providing a core substrate that includes a cavity, placing the device component in the cavity, forming a build-up film over the device component and the core substrate, forming a first contact via extending through the build-up film to contact the landing area and a second contact via extending through build-up film and the clearance opening, and performing a continuity test to determine whether the second contact via is in contact with the second pad.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 6, 2025
    Inventors: Wei-Hsuen Lee, Hung En Hsu, Kuo-Ching Hsu
  • Publication number: 20240387296
    Abstract: Methods of conducting electrical tests on semiconductor packages are provided. A method according to the present disclosure includes forming a build-up structure that includes a plurality of metal layers embedded a plurality of dielectric layers, forming a core structure that embeds a passive device, performing a first electrical test on the build-up structure, performing a second electrical test on the core structure, and after performing the first electrical test and the second electrical test, bonding the build-up structure to the core structure.
    Type: Application
    Filed: August 25, 2023
    Publication date: November 21, 2024
    Inventors: Ya Huei Lee, Ping Tai Chen, Kuo-Ching Hsu
  • Publication number: 20240387192
    Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate having a pad and a conductive adhesive layer over the pad and having a first inner wall, a second inner wall, a first sidewall, and a second sidewall. The first inner wall and the second inner wall face each other, and the first sidewall and the second sidewall are opposite to each other. The chip package structure also includes a nickel layer over the conductive adhesive layer, and the nickel layer covers the first inner wall, the second inner wall, the first sidewall, and the second sidewall of the conductive adhesive layer. The chip package structure further includes a chip over the wiring substrate and a conductive bump connected between the nickel layer and the chip.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Kuo-Ching HSU, Yu-Huan CHEN, Chen-Shien CHEN
  • Publication number: 20240379584
    Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Chih-Hsiang Tseng, Yu-Feng Chen, Cheng Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Kuo-Ching Hsu, Hong-Seng Shue, Ming-Hong Cha, Chao-Yi Wang, Mirng-Ji Lii
  • Patent number: 12125715
    Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate including a substrate, a first pad, and a second pad. The first pad and the second pad are respectively over a first surface and a second surface of the substrate, and the first pad is narrower than the second pad. The chip package structure includes a nickel layer over the first pad. The nickel layer has a T-shape in a cross-sectional view of the nickel layer. The chip package structure includes a chip over the wiring substrate. The chip package structure includes a conductive bump between the nickel layer and the chip.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Ching Hsu, Yu-Huan Chen, Chen-Shien Chen
  • Publication number: 20240321661
    Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.
    Type: Application
    Filed: May 30, 2024
    Publication date: September 26, 2024
    Inventors: Chen-Shien Chen, Kuo-Ching Hsu, Wei-Hung Lin, Hui-Min Huang, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20240312900
    Abstract: A chip package structure is provided. The chip package structure includes a first wiring substrate comprising a substrate, a first pad, a second pad, and an insulating layer. The first pad and the second pad are respectively over a first surface and a second surface of the substrate, the first surface is opposite to the second surface, the insulating layer is over the first surface and partially covers the first pad, and the first pad is wider than the second pad. The chip package structure includes a nickel-containing layer over the first pad. The chip package structure includes a conductive protection layer over the nickel-containing layer. The conductive protection layer has a curved surface, and a recess is surrounded by the curved surface and an inner wall of the insulating layer over the first pad.
    Type: Application
    Filed: May 28, 2024
    Publication date: September 19, 2024
    Inventors: Yu-Huan CHEN, Kuo-Ching HSU, Chen-Shien CHEN
  • Publication number: 20240274522
    Abstract: Embodiments provide a package substrate. The package substrate includes a substrate and a semiconductor device. The substrate includes a cavity hole therein. The semiconductor device is embedded in the cavity hole. The semiconductor device includes a first device component and a second device component. The first device component has a first pad, a second pad, and a first trench capacitor. The second device component has a third pad, a fourth pad, and a second trench capacitor. A backside of the first device component is bonded to a backside of the second device component, and the first pad has an area less than an area of the third pad, and the second pad has an area less than an area of the fourth pad.
    Type: Application
    Filed: April 25, 2024
    Publication date: August 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hungen Hsu, Wei-Tien Shen, Kuo-Ching Hsu
  • Publication number: 20240266266
    Abstract: A semiconductor structure includes: an interposer including an integrated passive device, a die-side redistribution structure, first on-interposer bump structures, and second on-interposer bump structures. First die-side redistribution wiring interconnects electrically connect electrical nodes within the integrated passive device to the first on-interposer bump structures. Second die-side redistribution wiring interconnects provide a respective electrical connection between a respective pair of second on-interposer bump structures. A first semiconductor die includes first on-die bump structures that are bonded to the first on-interposer bump structures through first solder material portions, and further includes second on-die bump structures that are bonded to the second on-interposer bump structures through second solder material portions.
    Type: Application
    Filed: May 24, 2023
    Publication date: August 8, 2024
    Inventors: Kuo-Ching Hsu, Hsiang-Tai Lu, Kuan-Lung Wu, Ya Huei Lee
  • Publication number: 20240266304
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.
    Type: Application
    Filed: April 17, 2024
    Publication date: August 8, 2024
    Inventors: Hao Chun Liu, Ching-Wen Hsiao, Kuo-Ching Hsu, Mirng-Ji Lii
  • Patent number: 12040266
    Abstract: Embodiments provide a package substrate. The package substrate includes a substrate having a cavity hole therein, and a semiconductor device in the cavity hole. The semiconductor device has first terminal side and a second terminal side opposite to the first terminal side. The package substrate further includes a first redistribution structure on the first terminal side of the cavity substrate to electrically couple to a first pad and a second pad on the first terminal side of the semiconductor device; and a second redistribution structure on the second side of the cavity substrate to electrically couple to a third pad and fourth pad on the second terminal side of the semiconductor device.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hungen Hsu, Wei-Tien Shen, Kuo-Ching Hsu
  • Patent number: 12027435
    Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: July 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Shien Chen, Kuo-Ching Hsu, Wei-Hung Lin, Hui-Min Huang, Ming-Da Cheng, Mirng-Ji Lii
  • Patent number: 12002746
    Abstract: A chip package structure is provided. The chip package structure includes a first wiring substrate including a substrate, a first pad, a second pad, and an insulating layer. The chip package structure includes a nickel-containing layer over the first pad. The chip package structure includes a conductive protection layer over the nickel-containing layer. The conductive protection layer includes tin, and a recess is surrounded by the conductive protection layer and the insulating layer over the first pad. The chip package structure includes a chip over the second surface of the substrate. The chip package structure includes a conductive bump between the second pad and the chip.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Huan Chen, Kuo-Ching Hsu, Chen-Shien Chen
  • Patent number: 11990428
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao Chun Liu, Ching-Wen Hsiao, Kuo-Ching Hsu, Mirng-Ji Lii
  • Publication number: 20240120277
    Abstract: A chip structure is provided. The chip structure includes a substrate, a redistribution layer over the substrate, a bonding pad over the redistribution layer, a shielding pad over the redistribution layer and surrounding the bonding pad, an insulating layer over the redistribution layer and the shielding pad, and a bump over the bonding pad and the insulating layer. The insulating layer includes a first part and a second part surrounded by the first part, the first part has first thickness, the second part has a second thickness, and the first thickness and the second thickness are different.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Inventors: Hong-Seng SHUE, Sheng-Han TSAI, Kuo-Chin CHANG, Mirng-Ji LII, Kuo-Ching HSU
  • Publication number: 20240096778
    Abstract: A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate supporting and electrically connected to the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment connected to the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 21, 2024
    Inventors: Ya-Huei LEE, Shu-Shen YEH, Kuo-Ching HSU, Shyue-Ter LEU, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20240021437
    Abstract: A laser-less packaging substrate fabrication process is provided. A substrate plate including through-plate metal via structures is provided. At least one interconnect-level structure may be formed by performing a unit sequence of processing steps that includes: a metal seed deposition step; a first masking step; a first electroplating step that forms metal lines; a second masking step; a second electroplating step that forms metal via structures; a seed layer etch step; a dielectric material deposition step that forms a dielectric material layer; and a planarization step that removes portions of the dielectric material layer that are more distal from the substrate plate than distal horizontal surfaces of the metal via structures. Laser drilling processing steps are not necessary during manufacture of the packaging substrate.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 18, 2024
    Inventors: Kuo-Ching HSU, Shyue-Ter LEU