Patents by Inventor Kuo-Ching Hsu
Kuo-Ching Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9312225Abstract: A bump structure that may be used for stacked die configurations is provided. Through-silicon vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon vias. The isolation film is thinned to re-expose the through-silicon vias. Bump pads and redistribution lines are formed on the backside of the semiconductor substrate providing an electrical connection to the through-silicon vias. Another isolation film is deposited and patterned, and a barrier layer is formed to provide contact pads for connecting to an external device, e.g., another die/wafer or circuit board.Type: GrantFiled: July 16, 2013Date of Patent: April 12, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Pin Chang, Kuo-Ching Hsu, Chen-Shien Chen, Wen-Chih Chiou, Chen-Hua Yu
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Patent number: 9299649Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.Type: GrantFiled: February 8, 2013Date of Patent: March 29, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Wei Chiu, Cheng-Hsien Hsieh, Hsien-Pin Hu, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng
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Publication number: 20150143324Abstract: Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern design. A routing pattern is designed based on the enhanced conductive bump pattern design. A design rule checking (DRC) procedure is performed on the routing pattern.Type: ApplicationFiled: November 20, 2013Publication date: May 21, 2015Inventors: Tzu-Yu Wang, Wei-Cheng Wu, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng
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Publication number: 20150061118Abstract: A three-dimensional chip stack includes a first chip bonded to a second chip to form a bonded interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.Type: ApplicationFiled: September 3, 2013Publication date: March 5, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Ming Chen, Cheng-Hsien Hsieh, Sung-Hui Huang, Kuo-Ching Hsu
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Publication number: 20150048503Abstract: A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias.Type: ApplicationFiled: August 16, 2013Publication date: February 19, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sao-Ling Chiu, Kuo-Ching Hsu, Wei-Cheng Wu, Ping-Kang Huang, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu
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Patent number: 8901735Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.Type: GrantFiled: January 22, 2014Date of Patent: December 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Ying Ching Shih, Po-Hao Tsai, Chin-Fu Kao, Cheng-Lin Huang, Cheng-Chieh Hsieh, Kuo-Ching Hsu, Jing-Cheng Lin, Shang-Yun Hou, Shin-Puu Jeng
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Patent number: 8871609Abstract: A thin wafer handling structure includes a semiconductor wafer, a release layer that can be released by applying energy, an adhesive layer that can be removed by a solvent, and a carrier, where the release layer is applied on the carrier by coating or laminating, the adhesive layer is applied on the semiconductor wafer by coating or laminating, and the semiconductor wafer and the carrier is bonded together with the release layer and the adhesive layer in between. The method includes applying a release layer on a carrier, applying an adhesive layer on a semiconductor wafer, bonding the carrier and the semiconductor wafer, releasing the carrier by applying energy on the release layer, e.g. UV or laser, and cleaning the semiconductor's surface by a solvent to remove any residue of the adhesive layer.Type: GrantFiled: June 18, 2010Date of Patent: October 28, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Kuo-Ching Hsu, Chen-Shien Chen, Ching-Wen Hsiao
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Publication number: 20140225277Abstract: An isolation structure for stacked dies is provided. A through-silicon via is formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon via. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon via. The isolation film is thinned to re-expose the through-silicon via, and conductive elements are formed on the through-silicon via. The conductive element may be, for example, a solder ball or a conductive pad. The conductive pad may be formed by depositing a seed layer and an overlying mask layer. The conductive pad is formed on the exposed seed layer. Thereafter, the mask layer and the unused seed layer may be removed.Type: ApplicationFiled: April 16, 2014Publication date: August 14, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Pin Chang, Kuo-Ching Hsu, Chen-Shien Chen, Wen-Chih Chiou, Chen-Hua Yu
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Publication number: 20140227831Abstract: A method of forming an integrated circuit structure is provided. The method includes providing a substrate, the substrate having a conductive pad thereon. A dielectric buffer layer is formed over at least a portion of the conductive pad, and an under-bump-metallurgy (UBM) is formed directly coupled to the conductive pad, wherein the UBM extends over at least a portion of the dielectric buffer layer. Thereafter, a conductive pillar is formed over the UBM, and one or more conductive materials are formed over the conductive pillar. The substrate may be attached to a carrier substrate using an adhesive.Type: ApplicationFiled: April 21, 2014Publication date: August 14, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hon-Lin Huang, Ching-Wen Hsiao, Kuo-Ching Hsu, Chen-Shien Chen
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Publication number: 20140225258Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.Type: ApplicationFiled: February 8, 2013Publication date: August 14, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Wei Chiu, Cheng-Hsien Hsieh, Hsien-Pin Hu, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng
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Patent number: 8759949Abstract: An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL.Type: GrantFiled: February 18, 2010Date of Patent: June 24, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hon-Lin Huang, Kuo-Ching Hsu, Chen-Shien Chen
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Publication number: 20140167254Abstract: A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The lateral dimension of the first metal pillar is greater than the lateral dimension of the second metal pillar.Type: ApplicationFiled: March 6, 2013Publication date: June 19, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Meng-Liang Lin, Jy-Jie Gau, Cheng-Lin Huang, Jing-Cheng Lin, Kuo-Ching Hsu
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Patent number: 8736050Abstract: An integrated circuit structure includes a semiconductor substrate; a conductive via (TSV) passing through the semiconductor substrate; and a copper-containing post overlying the semiconductor substrate and electrically connected to the conductive via.Type: GrantFiled: July 7, 2010Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hon-Lin Huang, Ching-Wen Hsiao, Kuo-Ching Hsu, Chen-Shien Chen
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Publication number: 20140131864Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.Type: ApplicationFiled: January 22, 2014Publication date: May 15, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Ying Ching Shih, Po-Hao Tsai, Chin-Fu Kao, Cheng-Lin Huang, Cheng-Chieh Hsieh, Kuo-Ching Hsu, Jing-Cheng Lin, Shang-Yun Hou, Shin-Puu Jeng
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Publication number: 20140130962Abstract: A method includes receiving a carrier with a release layer formed thereon. A first adhesive layer is formed on a wafer. A second adhesive layer is formed over the first adhesive layer or over the release layer. The carrier and the wafer are bonded with the release layer, the first adhesive layer, and the second adhesive layer in between the carrier and the wafer.Type: ApplicationFiled: January 16, 2014Publication date: May 15, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua YU, Kuo-Ching HSU, Chen-Shien CHEN, Ching-Wen HSIAO, Wen-Chih CHIOU, Shin-Puu JENG, Hung-Jung TU
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Patent number: 8670637Abstract: An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.Type: GrantFiled: August 12, 2011Date of Patent: March 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Cheng Chang, Jin-Lien Lin, Kuo-Ching Hsu, Kai-Ming Ching, Jiun Yi Wu, Yen-Huei Chen
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Patent number: 8664760Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.Type: GrantFiled: January 4, 2012Date of Patent: March 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Cheng-Chieh Hsieh, Kuo-Ching Hsu, Ying-Ching Shih, Po-Hao Tsai, Chin-Fu Kao, Cheng-Lin Huang, Jing-Cheng Lin
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Publication number: 20140038405Abstract: A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.Type: ApplicationFiled: October 3, 2013Publication date: February 6, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Kuo-Ching Hsu, Cheng-Chieh Hsieh, Ying-Ching Shih, Po-Hao Tsai, Cheng-Lin Huang, Jing-Cheng Lin
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Publication number: 20140014959Abstract: A packaged IC chip includes a testing pad, wherein the testing pad is electrically connected to devices in the packaged integrated circuit chip. The packaged IC chip further includes a first passivation layer over a portion of the testing pad, and a second passivation layer covering a surface of the testing pad and a portion of the first passivation layer surrounding the testing region of the testing pad. A distance between edges of the second passivation layer covering the surface of the testing pad to edges of the testing pad is in a range from about 2 mm to about 15 mm.Type: ApplicationFiled: September 17, 2013Publication date: January 16, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Puu JENG, Wei-Cheng WU, Shang-Yun HOU, Chen-Hua YU, Tzuan-Horng LIU, Tzu-Wei CHIU, Kuo-Ching HSU
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Patent number: 8610360Abstract: A light-emitting diode (LED) device for preventing soft-start flicker includes an LED module, a voltage converter, a variable current load and a loop control unit. The loop control unit is coupled to the LED module, the voltage converter and the variable current load, and includes a soft-start unit and a dimming control unit. The soft-start unit is utilized for activating a soft-start mechanism of the voltage converter when power of the LED device is turned on. The dimming control unit is utilized for controlling the variable current load to progressively increase a load current of the LED module to a target value and to maintain the load current on the target value until the soft-start mechanism is completed, so as to perform dimming control on the LED module.Type: GrantFiled: December 3, 2009Date of Patent: December 17, 2013Assignee: NOVATEK Microelectronics Corp.Inventors: Kuo-Ching Hsu, Chin-Hsun Hsu, Tsung-Hau Chang